System and method for correcting systematic parametric variations on integrated circuit chips in order to minimize circuit limited yield loss

Abstract

Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized.

1. A system for correcting systematic parametric variations on an integrated circuit chip, said system comprising:
 a process tool; 
 a data storage device storing a map of an integrated circuit chip, said integrated circuit chip having a given design and comprising a plurality of devices, said map indicating variations in a device parameter for said devices across different regions of said integrated circuit chip as a result of said given design, and said data storage device further storing information indicating a relative impact, on said device parameter, of changes in a specification associated with a process step performed by said process tool in manufacturing said integrated circuit chip according to said given design; 
 a processor accessing said data storage device and determining, based on said information and using said map as a guide, different values for said specification, each one of said different values for said specification to be used in a corresponding one of said different regions as said process step is performed by said process tool during said manufacturing of said integrated circuit chip according to said given design in order to offset said variations in said device parameter; and 
 a controller receiving said different values for said specification and controlling said process tool as said process step is performed by said process tool during said manufacturing of said integrated circuit chip according to said given design such that said different values for said specification are used in said different regions. 
 
     
     
       2. The system of  claim 1 , said map being generated empirically. 
     
     
       3. The system of  claim 1 , said map being generated based on modeling of said given design. 
     
     
       4. The system of  claim 1 , said device parameter comprising threshold voltage, said process tool comprising a laser anneal process tool and said specification comprising an anneal energy. 
     
     
       5. The system of  claim 1 , said device parameter comprising threshold voltage, said process tool comprising an ion implantation tool and said specification comprising a dopant dose. 
     
     
       6. A system for correcting systematic parametric variations on an integrated circuit chip, said system comprising:
 a laser anneal tool; 
 a data storage device storing a map of an integrated circuit chip, said integrated circuit chip having a given design and comprising a plurality of devices, said map indicating variations in threshold voltage for said devices across different regions of said integrated circuit chip as a result of said given design, said data storage device further storing information indicating a relative impact, on said threshold voltage, of changes in an amount of laser anneal energy associated with a laser anneal process performed by said laser anneal tool in manufacturing said integrated circuit chip according to said given design; 
 a processor accessing said data storage device and determining, based on said information and using said map as a guide, different laser anneal energy amounts, each one of said different laser anneal energy amounts to be used in a corresponding one of said different regions as said laser anneal process is performed by said laser anneal tool during said manufacturing of said integrated circuit chip according to said given design in order to offset said variations in said threshold voltage; and 
 a controller receiving said different values for said laser anneal energy and controlling said laser anneal tool as said laser anneal process is performed by said laser anneal tool during said manufacturing of said integrated circuit chip according to said given design such that said different values for said laser anneal energy are used in said different regions. 
 
     
     
       7. The system of  claim 6 , said map being generated empirically. 
     
     
       8. The system of  claim 6 , said map being generated based on modeling of said given design and said modeling accounting for at least one systematic, design-based phenomenon that impacts said threshold voltage. 
     
     
       9. The system of  claim 8 , said at least one systematic, design-based, phenomenon comprising any of regional variations in polysilicon perimeter density, regional variations in reflectance and absorption characteristics, and regional variations in voltage droop. 
     
     
       10. The system of  claim 6 , said laser anneal tool comprising a laser with an adjustable spot size to accommodate modulating laser anneal energy in said different regions. 
     
     
       11. The system of  claim 6 , said different laser anneal energy amounts comprising relatively high laser anneal energies for regions on said map having relatively high threshold voltages in order to decrease said relatively high threshold voltages and relatively low laser anneal energies for regions on said map having relatively low threshold voltages in order to increase said relatively low threshold voltages. 
     
     
       12. A method of correcting systematic parametric variations on an integrated circuit chip, said method comprising:
 generating, and storing in a data storage device, a map of an integrated circuit chip,
 said integrated circuit chip having a given design and comprising a plurality of devices, and 
 said map indicating variations in a device parameter for said devices across different regions of said integrated circuit chip as a result of said given design; 
 
 accessing, by a processor from said data storage device, said map and information indicating a relative impact, on said device parameter, of changes in a specification associated with a process step used in manufacturing said integrated circuit chip according to said given design; and 
 based on said information and using said map as a guide, determining, by said processor, different values for said specification, each one of said different values to be used in a corresponding one of said different regions as said process step is performed during said manufacturing of said integrated circuit chip according to said given design in order to offset said variations in said device parameter. 
 
     
     
       13. The method of  claim 12 , further comprising:
 receiving, by a controller, said different values for said specification; and 
 during manufacturing of said integrated circuit chip, controlling, by said controller, a process tool performing said process step such that said different values for said specification are used in said different regions. 
 
     
     
       14. The method of  claim 12 , said map being generated empirically. 
     
     
       15. The method of  claim 12 , said map being generated based on modeling of said given design. 
     
     
       16. The method of  claim 12 , said device parameter comprising threshold voltage, said process step comprising a laser anneal process and said specification comprising a laser anneal energy. 
     
     
       17. The method of  claim 12 , said device parameter comprising threshold voltage, said process step comprising an implantation process and said specification comprising a dopant dose. 
     
     
       18. A method of correcting systematic parametric variations on an integrated circuit chip, said method comprising:
 generating, and storing in a data storage device, a map of an integrated circuit chip,
 said integrated circuit chip having a given design and comprising a plurality of devices, and 
 said map indicating variations in threshold voltage for said devices across different regions of said integrated circuit chip as a result of said given design; 
 
 accessing, by a processor from said data storage device, said map and information indicating a relative impact, on said threshold voltage, of changes in an amount of laser anneal energy associated with a laser anneal process used in manufacturing said integrated circuit chip according to said given design; and 
 based on said information and using said map as a guide, determining, by said processor, different laser anneal energy amounts, each one of said different laser anneal energy amounts to be used in a corresponding one of said different regions as said laser anneal process is performed during manufacturing of said integrated circuit chip according to said given design in order to offset said variations in said threshold voltage. 
 
     
     
       19. The method of  claim 18 , further comprising:
 receiving, by a controller, said different laser anneal energy amounts; and 
 during manufacturing of said integrated circuit chip, controlling, by said controller, a laser anneal tool performing said laser anneal process such that said different laser anneal energy amounts are used in said different regions. 
 
     
     
       20. The method of  claim 18 , said map being generated empirically. 
     
     
       21. The method of  claim 18 , said map being generated based on modeling of said given design and said modeling accounting for at least one systematic, design-based, phenomenon that impacts said threshold voltage. 
     
     
       22. The method of  claim 21 , said at least one systematic, design-based, phenomenon comprising any of regional variations in polysilicon perimeter density, regional variations in reflectance and absorption characteristics, and regional variations in voltage droop. 
     
     
       23. The method of  claim 18 , further comprising, selectively adjusting a spot size of a laser in said laser anneal tool to accommodate modulating said laser anneal energy in said different regions. 
     
     
       24. The method of  claim 18 , said determining of said different laser anneal energy amounts comprising selecting relatively high laser anneal energies for regions on said map having relatively high threshold voltages in order to decrease said relatively high threshold voltages and selecting relatively low laser anneal energies for regions on said map having relatively low threshold voltages in order to increase said relatively low threshold voltages.