Inventor

PETERSON KIRK D

US141 patents

⚠️ This page may combine multiple inventors who share the name “PETERSON KIRK D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PETERSON KIRK D

IBM

Double planar gated SOI MOSFET structure

Double planar gated SOI MOSFET structure

Combined chemical mechanical polishing and reactive ion etching process

Photodiode structures

Sidewall image transfer (SIT) technologies

Method and structure to prevent circuit network charging during fabrication of integrated circuits

Halo implant in semiconductor structures

Plasma etch pre-silicide clean

Integrated cobalt silicide process for semiconductor devices

Photodiode structures

Photodiode structures

Lateral non-volatile storage cell

Photodiode structures

Semiconductor via structure with lower electrical resistance

Optimized wires for resistance or electromigration

Encapsulated sensors

Vertical bend waveguide coupler for photonics applications

High dynamic range imaging cell with electronic shutter extensions

Structure for a phase locked loop with adjustable voltage based on temperature

High dynamic range imaging cell with electronic shutter extensions

Adjusting voltage for a phase locked loop based on temperature

Protect diodes for hybrid-orientation substrate structures

Immunity to inline charging damage in circuit designs

Power gating and clock gating in wiring levels

Multiple precipitation doping process

Contacts having a geometry to reduce resistance

Managed integrated circuit power supply distribution

Low resistance contact for transistors

Semiconductor via structure with lower electrical resistance

Deterministic current based frequency optimization of processor chip

Deterministic current based frequency optimization of processor chip

Waveguide switch with tuned photonic microring

Semiconductor-on-insulator (SOI) deep trench capacitor

Vertically curved waveguide

Voltage identifier sorting

Method for fabricating doped polysilicon lines

On chip electrostatic discharge (ESD) event monitoring

Structure and method for formation of a blocked silicide resistor

Circuit design for balanced logic stress

TEXAS INSTRUMENTS INC

Focal plane array integrated circuit with individual pixel signal processing

Analog to digital video converter

Uncooled infrared detector readout monolithic integrated circuit with individual pixel signal processing

Dual voltage level shifted, cascoded current mirror

Dual voltage level shifted, cascoded current mirror

Charge pump with switched capacitor feedback

Resistor string DAC with improved speed

BRACERAS GEORGE M

Dual power supply memory array having a control circuit that dynamically selects a lower of two supply voltages for bitline pre-charge operations and an associated method

GERVAIS GILLES

Optimizing voltage on a power plane using a networked voltage regulation module array

DRS RSTA INC

High density capacitor integrated into focal plane array processing flow

DRS TECHNOLOGIES INC

Focal plane array integrated circuit with individual pixel signal processing