Resistor string DAC with improved speed

Abstract

The speed performance of a resistive DAC can be improved by tailoring the selection switch size to the node location. For the simple case of a DAC used in a SAR-based ADC, the MSB code, which is activated during each SAR search, is the speed-limiting bit. Increasing the size of the switch on the node corresponding to the MSB will reduce the on-resistance of the FET and, therefore, the total resistance to ground from the node. The on-resistance can be changed markedly without substantially changing the total capacitance at the output node, since the sum of the parasitic from the remaining switches will far exceed the additional capacitance created by increasing the MSB FET.

What is claimed: 
     
       1. A resistor string digital to analog converter, comprising: a decoder having a plurality of analog outputs, one of which is for the most significant bit of the analog out;   a plurality of selection switches connected to a reference voltage and each switch connected to an analog voltage output from the decoder, including a voltage representative of the most significant digital bit;   each switch having a switch resistance; and   the resistance of the switch for the most significant bit being less in magnitude that the resistance of the other switches.   
     
     
       2. The resistor string digital to analog converter according to claim 1, wherein the resistance of the switch for the most significant bit is one-half of the value for the remaining switches. 
     
     
       3. The resistor string digital to analog converter according to claim 1, wherein two of the plurality selection switches have a resistance less that the remaining switches, and a greater resistance than the switch for the most significant bit. 
     
     
       4. A resistor string digital to analog converter, comprising: a decoder having a plurality of analog outputs, one of which is for the most significant bit of the analog out;   a plurality of selection switches connected to a reference voltage and each switch connected to an analog voltage output from the decoder, including a voltage representative of the most significant digital bit;   each switch constructed with a N-CMOS device and P-CMOS device which form a switch resistance, the switch resistance for the switch for the most significant bit being less than the resistance for the other plurality of selection switches.   
     
     
       5. The resistor string digital to analog converter according to claims 4, wherein each switch N-CMOS and P-CMOS device has a channel width and length, the channel width and length of the P-CMOS and N-CMOS devices for the most significant bit switch being different from the channel widths and lengths of the non-most significant bit switches. 
     
     
       6. The resistor string digital to analog converter according to claim 5, wherein the Width/Length ratio of the non-most significant bit switches is 10/1 and the Width/Length ratio for the most significant bit switches is 20/1.