Inventor
DESOTA DONALD R
US29 patents
⚠️ This page may combine multiple inventors who share the name “DESOTA DONALD R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
21 patentsUS6295584B1Sep 25, 2001
Multiprocessor computer system with memory map translation
IBM79 citations95
US6971041B2Nov 29, 2005
Cache entry error-correcting code (ECC) based at least on cache entry data and memory address
IBM22 citations92
US6829679B2Dec 7, 2004
Different caching treatment of memory contents based on memory region
IBM31 citations92
US7272754B2Sep 18, 2007
Implementation-efficient multiple-counter value hardware performance counter
IBM27 citations90
US7337352B2Feb 26, 2008
Cache entry error-connecting code (ECC) based at least on cache entry data and memory address
IBM15 citations84
US9317427B2Apr 19, 2016
Reallocating unused memory databus utilization to another processor when utilization is below a threshold
IBM8 citations82
US9098351B2Aug 4, 2015
Energy-aware job scheduling for cluster environments
IBM9 citations82
US6848026B2Jan 25, 2005
Caching memory contents into cache partitions based on memory locations
IBM13 citations82
US7383464B2Jun 3, 2008
Non-inline transaction error correction
IBM6 citations73
US7861126B2Dec 28, 2010
Implementation-efficient multiple-counter value hardware performance counter
IBM5 citations71
US7827449B2Nov 2, 2010
Non-inline transaction error correction
IBM2 citations62
US7594080B2Sep 22, 2009
Temporary storage of memory line while waiting for cache eviction
IBM5 citations62
US7210018B2Apr 24, 2007
Multiple-stage pipeline for transaction conversion
IBM3 citations62
US6996665B2Feb 7, 2006
Hazard queue for transaction pipeline
IBM4 citations62
US8015248B2Sep 6, 2011
Queuing of conflicted remotely received transactions
IBM1 citations61
US7529800B2May 5, 2009
Queuing of conflicted remotely received transactions
IBM4 citations61
US7437622B2Oct 14, 2008
Implementation-efficient multiple-counter value hardware performance counter
IBM3 citations60
US7395375B2Jul 1, 2008
Prefetch miss indicator for cache coherence directory misses on external caches
IBM3 citations59
US7089372B2Aug 8, 2006
Local region table for storage of information regarding memory access by other nodes
IBM5 citations58
US7194585B2Mar 20, 2007
Coherency controller management of transactions
IBM0 citations51
US7669010B2Feb 23, 2010
Prefetch miss indicator for cache coherence directory misses on external caches
IBM1 citations48
DESOTA DONALD R
3 patentsUS8578130B2Nov 5, 2013
Partitioning of node into more than one partition
DESOTA DONALD R17 citations81
US8898674B2Nov 25, 2014
Memory databus utilization management system and computer program product
DESOTA DONALD R0 citations48
US8589656B2Nov 19, 2013
Queuing of conflicted remotely received transactions
DESOTA DONALD R0 citations48