Inventor · disambiguated record
Jon Robert Tetzloff
Also filed as: TETZLOFF JON R · TETZLOFF JON ROBERT
11 granted patents·2 pending applications·293 citations·filing 2004–2019
89Inventor score
Files withIBM13
Top patents by PatentIndex Score
13 records- 0197US7227183B2Polysilicon conductor width measurement for 3-dimensional FETsIBM·Filed 2004·Granted Jun 5, 2007·197 cites·11 claims
- 0294US7183780B2Electrical open/short contact alignment structure for active region vs. gate regionIBM·Filed 2004·Granted Feb 27, 2007·62 cites·3 claims
- 0375US7241649B2FinFET body contact structureIBM·Filed 2004·Granted Jul 10, 2007·18 cites·14 claims
- 0468US7696565B2FinFET body contact structureIBM·Filed 2007·Granted Apr 13, 2010·3 cites·5 claims
- 0560US7317605B2Method and apparatus for improving performance margin in logic pathsIBM·Filed 2004·Granted Jan 8, 2008·11 cites·8 claims
- 0654US7453272B2Electrical open/short contact alignment structure for active region vs. gate regionIBM·Filed 2006·Granted Nov 18, 2008·0 cites·6 claims
- 0754US7336086B2Measurement of bias of a silicon area using bridging vertices on polysilicon shapes to create an electrical open/short contact structureIBM·Filed 2006·Granted Feb 26, 2008·0 cites·3 claims
- 0853US11422611B2Adaptive frequency optimization in processorsIBM·Filed 2019·Granted Aug 23, 2022·0 cites·20 claims
- 0952US7659733B2Electrical open/short contact alignment structure for active region vs. gate regionIBM·Filed 2006·Granted Feb 9, 2010·0 cites·3 claims
- 1051US10509457B2Adaptive frequency optimization in processorsIBM·Filed 2017·Granted Dec 17, 2019·0 cites·17 claims
- 1150US2007128740A1Polysilicon Conductor Width Measurement for 3-Dimensional FETsIBM·Filed 2007·Application pending·0 cites
- 1248US8049526B2Enhanced speed sorting of microprocessors at wafer testIBM·Filed 2008·Granted Nov 1, 2011·2 cites·16 claims
- 1335US2006063334A1Fin FET diode structures and methods for buildingIBM·Filed 2004·Application pending·0 cites
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