Polysilicon Conductor Width Measurement for 3-Dimensional FETs

Abstract

An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon “fins”. A first resistor has a first line width. A second resistor has a second line width. The second line width is slightly different than the first line width. Advantageously, the first line width is equal to the nominal design width used to make FET gates in the particular semiconductor technology. Resistance measurements of the resistors and subsequent calculations using the resistance measurements are used to determine the actual polysilicon conductor width produced by the semiconductor process. A composite test structure not only allows calculation of the polysilicon conductor width, but provides proof that differences in the widths used in the calculations do not introduce objectionable etching characteristics of the polysilicon conductors.

1 . A method of determining a finished width of a polysilicon conductor routed over fins of a FinFET on a semiconductor chip comprising the steps of: 
 creating one or more semiconductor fins on a semiconductor chip;    constructing a first resistor having one or more fingers having a first design width, the fingers constructed of polysilicon and routed, at least in part, substantially orthogonally over the one or more fins;    constructing a second resistor having one or more fingers having a second design width that is different from the first design width, the fingers constructed of polysilicon and routed, at least in part, orthogonally over the one or more fins;    measuring a first resistance value of the first resistor;    measuring a second resistance value of the second resistor; and    determining the finished width of the first design width, using the first design width, the second design width, the first resistance value and the second resistance value.    
   
   
       2 . The method of  claim 1 , further comprising the step of ensuring that the one or more fingers of the first resistor have substantially the same process each properties as the one or more fingers of the second resistor.  
   
   
       3 . The method of  claim 2 , further comprising the steps of: 
 creating one or more additional resistors having one or more fingers having design widths different enough from the first design width and the second design width to provide information as to design widths that result in different polysilicon etch characteristics from the first design width and the second design width, the fingers constructed of polysilicon and routed, at least in part, orthogonally over the one or more fins;    measuring resistance values of the one or more additional resistors;    determining estimates of the finished width of the first design width using the resistance values of the one or more additional resistors and the resistance value of the first resistor; and    determining a maximum design width difference.    
   
   
       4 . The method of  claim 3 , the step of determining a maximum design width difference further comprising the step of creating the one or more additional resistors having design width differences beyond which a determination of the finished width of the first design width differ from determination of the finished width of the first design width using design widths less than the maximum design width difference by a predetermined amount.  
   
   
       5 . The method of  claim 1 , further comprising the steps of: 
 constructing a third resistor having one or more fingers having a third design width that is different from the first design width and different from the second design width, the fingers constructed of polysilicon and routed, at least in part,    orthogonally over the one or more fins;    measuring a third resistance value of the third resistor;    determining the finished width of the first design width, using the first design width, the second design width, the third design width, the first resistance value, the second resistance value, and the third resistance value.