Inventor

LUO ZHIJIONG

US192 patents

⚠️ This page may combine multiple inventors who share the name “LUO ZHIJIONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LUO ZHIJIONG

IBM

Methods of forming semiconductor devices using embedded L-shape spacers

finFET structure with multiply stressed gate electrode

Method for forming self-aligned dual salicide in CMOS technologies

N-channel MOSFETs comprising dual stressors, and methods for forming the same

Structure and method to form multilayer embedded stressors

Device having self-aligned double gate formed by backside engineering, and device having super-steep retrograded island

Dual stress memory technique method and related structure

Forming silicided gate and contacts from polysilicon germanium and structure formed

Methods for forming dual fully silicided gates over fins of FinFet devices

SOI substrates and SOI devices, and methods for forming the same

SOI field effect transistor having asymmetric junction leakage

Structure and method to form multilayer embedded stressors

Method and structure to form self-aligned selective-SOI

Method of forming substantially L-shaped silicide contact for a semiconductor device

MOSFETs comprising source/drain regions with slanted upper surfaces, and method for fabricating the same

Embedded insulating band for controlling short-channel effect and leakage reduction for DSB process

Semiconductor structure including laminated isolation region

Fully silicided field effect transistors

Method for forming self-aligned dual salicide in CMOS technologies

Self-forming metal silicide gate for CMOS devices

ZHU HUILONG

Semiconductor device and method for manufacturing the same

Method for manufacturing graphene nano-ribbon, mosfet and method for manufacturing the same

Method for fabricating contact electrode and semiconductor device

Method for making FINFETs and semiconductor structures formed therefrom

Semiconductor device and method for manufacturing the same

FinFET and method for manufacturing the same

Structure and method having asymmetrical junction or reverse halo profile for semiconductor on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET)

Structure and method having asymmetrical junction or reverse halo profile for semiconductor on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET)

FinFET structure with multiply stressed gate electrode

YIN HAIZHOU

Transistor with primary and semiconductor spacer, method for manufacturing transistor, and semiconductor chip comprising the transistor

Gate stack structure, semiconductor device and method for manufacturing the same

Hybrid channel semiconductor device and method for forming the same

Semiconductor structure and method for manufacturing the same

Semiconductor structure and method for manufacturing the same

Method for forming a semiconductor device with stressed trench isolation

Structure of high-K metal gate semiconductor transistor

CHARTERED SEMICONDUCTOR MFG

Formation of raised source/drain structures in NFET with embedded SiGe in PFET

Method to form selective strained Si using lateral epitaxy

Method of fabricating a transistor structure

LUO ZHIJIONG

Fin transistor structure and method of fabricating the same

Fin transistor structure and method of fabricating the same

Inducing stress in CMOS device

FAROOQ MUKTA G

Bonded structure employing metal semiconductor alloy bonding

Bonded structure with enhanced adhesion strength

CHONG YUNG FU

Method to control source/drain stressor profiles for stress engineering

Formation of raised source/drain structures in NFET with embedded SiGe in PFET

ASPIRING SKY CO LTD

SRAM based memory structures and methods thereof

Hybrid non-volatile memory devices with static random access memory (SRAM) array and non-volatile memory (NVM) array

GLOBALFOUNDRIES SG PTE LTD

Method to control source/drain stressor profiles for stress engineering

SAMSUNG ELECTRONICS CO LTD

Embedded stressor structure and process