Inventor

BAARS PETER

DE107 patents

⚠️ This page may combine multiple inventors who share the name “BAARS PETER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BAARS PETER

GLOBALFOUNDRIES INC

Methods of forming a semiconductor circuit element and semiconductor circuit element

Semiconductor device including buried capacitive structures and a method of forming the same

Semiconductor structure including a nonvolatile memory cell and method for the formation thereof

Junction formation with reduced CEFF for 22NM FDSOI devices

Methods of forming semiconductor devices comprising ferroelectric elements and fast high-K metal gate transistors

Semiconductor devices with replacement gate structures having conductive contacts positioned therebetween

Methods of forming semiconductor devices with replacement gate structures

Semiconductor structure including a nonvolatile memory cell having a charge trapping layer and method for the formation thereof

Methods for fabricating integrated circuits

Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

Contact scheme for landing on different contact area levels

Circuits constructed from stacked field-effect transistors

Junction formation with reduced Ceff for 22nm FDSOI devices

FDSOI—capacitor

Semiconductor device comprising ferroelectric elements and fast high-K metal gate transistors

Compact FDSOI device with Bulex contact extending through buried insulating layer adjacent gate structure for back-bias

FDSOI semiconductor device with contact enhancement layer and method of manufacturing

Methods of forming a semiconductor circuit element and semiconductor circuit element

Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dial raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

Semiconductor device comprising trench isolation

Fully depleted device with buried insulating layer in channel region

Embedded capacitor

Replacement gate fabrication methods

Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions

Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask

Semiconductor device with interconnect to source/drain

BAARS PETER

Methods for forming semiconductor devices

SRAM integrated circuits with buried saddle-shaped FINFET and methods for their fabrication

Method of forming self-aligned contacts for a semiconductor device

Semiconductor device comprising replacement gate electrode structures and self-aligned contact elements formed by a late contact fill

Encapsulation of closely spaced gate electrode structures

Semiconductor device with DRAM bit lines made from same material as gate electrodes in non-memory regions of the device, and methods of making same

Semiconductor device comprising a capacitor formed in the metallization system based on dummy metal features

Integrated circuits that include deep trench capacitors and methods for their fabrication

Replacement gate fabrication methods

Semiconductor device with embedded low-K metallization

QIMONDA AG

Memory devices including semiconductor pillars

Semiconductor component with MIM capacitor

Integrated circuit and methods of manufacturing the same

GLOBALFOUNDRIES US INC

Extended-drain metal-oxide-semiconductor devices with a silicon-germanium layer beneath a portion of the gate

Semiconductor device with novel spacer structures having novel configurations

Semiconductor device with interconnect to source/drain

WEI ANDY

Fin-transistor formed on a patterned STI region by late fin etch

Method of forming a semiconductor device by using sacrificial gate electrodes and sacrificial self-aligned contact structures

SCHLOESSER TILL

Semiconductor device comprising self-aligned contact elements and a replacement gate electrode structure

WEI ANDY C

Methods for fabricating integrated circuits

INFINEON TECHNOLOGIES AG

Method of manufacturing a field effect transistor device with recessed channel and corner gate device

WERNER THOMAS

Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions

SCHEIPER THILO

Superior integrity of high-k metal gate stacks by capping STI regions

JAKUBOWSKI FRANK

STI silicon nitride cap for flat FEOL topology