Inventor

GREENE ANDREW M

US107 patents

⚠️ This page may combine multiple inventors who share the name “GREENE ANDREW M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GREENE ANDREW M

IBM

Fin cut during replacement gate formation

Cutting fins and gates in CMOS devices

Gate cut with integrated etch stop layer

Trench silicide contacts with high selectivity process

Gate cut with high selectivity to preserve interlevel dielectric layer

Gate cut in RMG

Gate cut in RMG

Fin cut during replacement gate formation

Gate height control and ILD protection

Gate cut with high selectivity to preserve interlevel dielectric layer

Self-aligned local interconnect technology

Self aligned gate shape preventing void formation

POC process flow for conformal recess fill

Trench formation for dielectric filled cut region

Trench formation for dielectric filled cut region

POC process flow for conformal recess fill

POC process flow for conformal recess fill

FinFET gate cut after dummy gate removal

FinFET device formed by a replacement metal-gate method including a gate cut-last step

Vertical FET replacement gate formation with variable fin pitch

Gate-all-around monolithic stacked field effect transistors having multiple threshold voltages

Nanosheet transistor device with bottom isolation

Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)

Gate cut device fabrication with extended height gates

Fin cut to prevent replacement gate collapse on STI

Gate cut using selective deposition to prevent oxide loss

Gate cut with integrated etch stop layer

Gate cut device fabrication with extended height gates

Self aligned gate shape preventing void formation

Gate cut using selective deposition to prevent oxide loss

Self-aligned local interconnect technology

Fin cut during replacement gate formation

Forming self-aligned contact with spacer first

HDP fill with reduced void formation and spacer damage

Additive core subtractive liner for metal cut etch processes

Semiconductor device replacement metal gate with gate cut last in RMG

Semiconductor device with linerless contacts

Field effect transistors with bottom dielectric isolation

Gate-all-around field-effect-transistor with wrap-around-channel inner spacer

Strain generation and anchoring in gate-all-around field effect transistors

Late replacement bottom isolation for nanosheet devices

Nanosheet transistor with enhanced bottom isolation

Planar devices with consistent base dielectric

TESSERA LLC

Gate cut with integrated etch stop layer

Gate cut with integrated etch stop layer

Gate cut with integrated etch stop layer

TESSERA INC

Gate cut with integrated etch stop layer

FinFET gate cut after dummy gate removal

ADEIA SEMICONDUCTOR SOLUTIONS LLC

FinFET gate cut after dummy gate removal

GLOBALFOUNDRIES INC

Method to increase effective gate height