FinFET gate cut after dummy gate removal

Abstract

Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a first semiconductor fin;   a first gate stack formed over the first semiconductor fin;   source and drain regions formed on respective sides of the first gate stack;   an interlayer dielectric formed around the first gate stack; and   a gate cut plug, formed from a dielectric material at an end of the first gate stack, comprising a first layer of dielectric material and a second layer of planarizing material.   
     
     
       2. The semiconductor device of  claim 1 , wherein the gate cut plug has a vertical profile. 
     
     
       3. The semiconductor device of  claim 1 , further comprising a second semiconductor fin parallel to the first semiconductor fin. 
     
     
       4. The semiconductor device of  claim 1 , further comprising a second gate stack formed over the second semiconductor fin and in line with the first gate stack. 
     
     
       5. The semiconductor device of  claim 4 , wherein the gate cut plug completely fills a space between the first gate stack and the second gate stack. 
     
     
       6. The semiconductor device of  claim 1 , wherein the first layer of dielectric material is formed conformally on spacer sidewalls but does not fill the space between the spacer sidewalls. 
     
     
       7. The semiconductor device of  claim 6 , wherein the second layer of planarizing material completely fills any space between the spacer sidewalls that is not filled by the first layer of dielectric material. 
     
     
       8. The semiconductor device of  claim 7 , wherein the first layer of dielectric material is formed from silicon nitride and wherein the second layer of planarizing material is formed from silicon dioxide. 
     
     
       9. A semiconductor device, comprising:
 a first semiconductor fin;   a first gate stack formed over the first semiconductor fin;   source and drain regions formed on respective sides of the first gate stack;   an interlayer dielectric formed around the first gate stack; and   a gate cut plug, comprising a first layer of dielectric material formed conformally on spacer sidewalls and a second layer of planarizing material that completely fills any space between the spacer sidewalls that is not filled by the first layer of dielectric material, at an end of the first gate stack.   
     
     
       10. The semiconductor device of  claim 9 , wherein the gate cut plug has a vertical profile. 
     
     
       11. The semiconductor device of  claim 9 , further comprising a second semiconductor fin parallel to the first semiconductor fin. 
     
     
       12. The semiconductor device of  claim 9 , further comprising a second gate stack formed over the second semiconductor fin and in line with the first gate stack. 
     
     
       13. The semiconductor device of  claim 12 , wherein the gate cut plug completely fills a space between the first gate stack and the second gate stack. 
     
     
       14. The semiconductor device of  claim 9 , wherein the first layer of dielectric material is formed from silicon nitride and wherein the second layer of planarizing material is formed from silicon dioxide. 
     
     
       15. A semiconductor device, comprising:
 a first semiconductor fin;   a first gate stack formed over the first semiconductor fin;   source and drain regions formed on respective sides of the first gate stack;   an interlayer dielectric formed around the first gate stack; and   a gate cut plug, comprising a first layer of silicon nitride formed conformally on spacer sidewalls and a second layer of silicon dioxide that completely fills any space between the spacer sidewalls that is not filled by the first layer of silicon nitride, at an end of the first gate stack.   
     
     
       16. The semiconductor device of  claim 15 , wherein the gate cut plug has a vertical profile. 
     
     
       17. The semiconductor device of  claim 15 , further comprising a second semiconductor fin parallel to the first semiconductor fin. 
     
     
       18. The semiconductor device of  claim 15 , further comprising a second gate stack formed over the second semiconductor fin and in line with the first gate stack. 
     
     
       19. The semiconductor device of  claim 18 , wherein the gate cut plug completely fills a space between the first gate stack and the second gate stack. 
     
     
       20. A semiconductor device, comprising:
 a first gate plug feature disposed between and in-line with a first gate stack and a second gate stack, wherein the first gate plug feature, the first gate stack, and the second gate stack all extend in a first direction; and   a third gate stack disposed adjacent to the first gate plug feature and spaced apart from the first gate plug feature in a second direction perpendicular to the first direction, wherein:
 the third gate stack extends in the first direction; 
 the first gate stack, the second gate stack, and the third gate stack each comprise a gate dielectric; 
 the gate dielectric of the first gate stack lines a first sidewall of the first gate plug feature; 
 the gate dielectric of the second gate stack lines a second sidewall of the first gate plug feature; 
 the first gate plug feature comprises:
 a first dielectric material disposed on a bottom of a trench and on opposing sides of the trench in both the first direction and the second direction; and 
 a second dielectric planarizing material disposed on the first dielectric material and between the first dielectric material disposed on the opposing sides of the trench in both the first direction and the second direction; and 
 
 the gate dielectric of the first gate stack comprises a high-k dielectric layer disposed between conductive portions of the first gate stack and the first gate plug feature. 
   
     
     
       21. The semiconductor device of  claim 20 , comprising a second gate plug feature disposed adjacent to the first gate plug feature and opposite the third gate stack. 
     
     
       22. The semiconductor device of  claim 20 , comprising a fourth gate stack disposed adjacent to the third gate stack. 
     
     
       23. The semiconductor device of  claim 20 , wherein the first dielectric material is conformal. 
     
     
       24. The semiconductor device of  claim 20 , wherein the first dielectric material comprises a nitride. 
     
     
       25. The semiconductor device of  claim 20 , wherein the first dielectric material comprises silicon nitride. 
     
     
       26. The semiconductor device of  claim 20 , wherein the second dielectric planarizing material comprises an oxide. 
     
     
       27. The semiconductor device of  claim 20 , wherein the second dielectric planarizing material comprises a silicon oxide. 
     
     
       28. The semiconductor device of  claim 20 , wherein the first gate stack, the second gate stack, and the third gate stack each comprise a work function metal layer. 
     
     
       29. The semiconductor device of  claim 20 , wherein the first gate stack, the second gate stack, and the third gate stack each comprise a gate conductor. 
     
     
       30. The semiconductor device of  claim 29 , wherein each gate conductor comprises at least one of tungsten, nickel, titanium, molybdenum, tantalum, copper, platinum, silver, gold, ruthenium, iridium, rhenium, rhodium. 
     
     
       31. The semiconductor device of  claim 20 , wherein each of the first gate stack, the second gate stack, and the first gate plug feature are disposed between gate spacers extending continuously in the first direction. 
     
     
       32. The semiconductor device of  claim 31 , wherein the gate spacers comprise a nitride. 
     
     
       33. The semiconductor device of  claim 31 , wherein the gate spacers comprise silicon nitride. 
     
     
       34. The semiconductor device of  claim 31 , wherein the gate spacers comprise carbon. 
     
     
       35. The semiconductor device of  claim 31 , wherein the gate spacers comprise boron. 
     
     
       36. The semiconductor device of  claim 31 , wherein the gate spacers comprise SiOCN. 
     
     
       37. The semiconductor device of  claim 31 , wherein the gate spacers comprise SiBCN. 
     
     
       38. The semiconductor device of  claim 20 , wherein the first gate plug feature is substantially coplanar with a conductive upper surface of the first gate stack.