Assignee
ADEIA SEMICONDUCTOR SOLUTIONS LLC
US·34 granted patents·14 pending applications·15 citations·filing 2020–2025
Top patents by PatentIndex Score
48 records- 0198US12154971B2Forming nanosheet transistor using sacrificial spacer and inner spacersADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Nov 26, 2024·2 cites·20 claims
- 0298US11784095B2Fabrication of a vertical fin field effect transistor with reduced dimensional variationsADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Oct 10, 2023·2 cites·20 claims
- 0397US12218003B2Selective ILD deposition for fully aligned via with airgapADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Feb 4, 2025·2 cites·20 claims
- 0497US11830845B2Package-on-package assembly with wire bonds to encapsulation surfaceADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Nov 28, 2023·4 cites·19 claims
- 0596US2026013208A1Selective removal of semiconductor finsADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2025·Application pending·0 cites
- 0695US11955424B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Apr 9, 2024·1 cites·20 claims
- 0792US11894462B2Forming a sacrificial liner for dual channel devicesADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2021·Granted Feb 6, 2024·1 cites·20 claims
- 0892US2025142938A1Fabrication of a vertical fin field effect transistor with reduced dimensional variationsADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2024·Application pending·0 cites
- 0991USRE50613EFinFET gate cut after dummy gate removalADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Sep 30, 2025·1 cites·38 claims
- 1091US11837501B2Selective recessing to form a fully aligned viaADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Dec 5, 2023·1 cites·26 claims
- 1191US2025142855A1Punch through stopper in bulk finfet deviceADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2024·Application pending·0 cites
- 1291US2025142856A1Nanosheet channel-to-source and drain isolationADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2024·Application pending·0 cites
- 1390US2025140611A1Selective recessing to form a fully aligned viaADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2024·Application pending·0 cites
- 1489US12550359B2Forming a sacrificial liner for dual channel devicesADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Feb 10, 2026·0 cites·20 claims
- 1589US12136573B2Fabrication of a vertical fin field effect transistor with reduced dimensional variationsADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Nov 5, 2024·0 cites·22 claims
- 1689US2025140606A1Selective ild deposition for fully aligned via with airgapADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2024·Application pending·0 cites
- 1789US2025142921A1Forming nanosheet transistor using sacrificial spacer and inner spacersADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2024·Application pending·0 cites
- 1888US12327730B2Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logicADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2024·Granted Jun 10, 2025·0 cites·22 claims
- 1988US11901438B2Nanosheet transistorADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2021·Granted Feb 13, 2024·1 cites·20 claims
- 2087US12550709B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2024·Granted Feb 10, 2026·0 cites·20 claims
- 2187US12520567B2Hybrid-channel nano-sheet FETsADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Jan 6, 2026·0 cites·20 claims
- 2287US12376369B2FinFET devicesADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Jul 29, 2025·0 cites·18 claims
- 2387US12369379B2Nanosheet transistorADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Jul 22, 2025·0 cites·20 claims
- 2487US2024387264A1Advanced copper interconnects with hybrid microstructureADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Application pending·0 cites
- 2587US2026101694A1Two-color self-aligned double patterning (sadp) to yield static random access memory (sram) and dense logicADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2025·Application pending·0 cites
- 2687US2026090305A1Alternating hardmasks for tight-pitch line formationADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2025·Application pending·0 cites
- 2786US12166110B2Nanosheet channel-to-source and drain isolationADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Dec 10, 2024·0 cites·23 claims
- 2886US2025132199A1Structure and method to improve fav rie process margin and electromigrationADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2024·Application pending·0 cites
- 2986US2024006237A1Method of forming copper interconnect structure with manganese barrier layerADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Application pending·0 cites
- 3085US12322601B2Alternating hardmasks for tight-pitch line formationADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Jun 3, 2025·0 cites·22 claims
- 3185US12237328B2Minimizing shorting between FinFET epitaxial regionsADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Feb 25, 2025·0 cites·16 claims
- 3285US12224203B2Air gap spacer formation for nano-scale semiconductor devicesADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Feb 11, 2025·0 cites·20 claims
- 3384US12532682B2Method of manufacturing a structure by asymmetrical ion bombardment of a capped underlying layerADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Jan 20, 2026·0 cites·22 claims
- 3484US12237368B2Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stackADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Feb 25, 2025·0 cites·19 claims
- 3583US12230544B2Stacked transistors with different channel widthsADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Feb 18, 2025·0 cites·19 claims
- 3683US12119393B2Punch through stopper in bulk finFET deviceADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Oct 15, 2024·0 cites·20 claims
- 3782US12402403B2Air gap spacer for metal gatesADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Aug 26, 2025·0 cites·20 claims
- 3882US12183634B2Selective recessing to form a fully aligned viaADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Dec 31, 2024·0 cites·22 claims
- 3980US12369367B2Bulk nanosheet with dielectric isolationADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Jul 22, 2025·0 cites·20 claims
- 4080US11881433B2Advanced copper interconnects with hybrid microstructureADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2021·Granted Jan 23, 2024·0 cites·19 claims
- 4180US2025169171A1Minimizing shorting between finfet epitaxial regionsADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2025·Application pending·0 cites
- 4279US12488986B2Selective gas etching for self-aligned pattern transferADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Dec 2, 2025·0 cites·10 claims
- 4379US12482704B2Self-forming barrier for use in air gap formationADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Nov 25, 2025·0 cites·19 claims
- 4479US12387983B2Forming self-aligned vias and air-gaps in semiconductor fabricationADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2022·Granted Aug 12, 2025·0 cites·19 claims
- 4578US2025169157A1Stacked transistors with different channel widthsADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2025·Application pending·0 cites
- 4673US12598786B2Field effect transistor structuresADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2021·Granted Apr 7, 2026·0 cites·21 claims
- 4772US12494453B2Package-on-package assembly with wire bonds to encapsulation surfaceADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Dec 9, 2025·0 cites·16 claims
- 4871USRE49794ESRAM design to facilitate single fin cut in double sidewall image transfer processADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2020·Granted Jan 9, 2024·0 cites·36 claims
Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →