Nanosheet transistor

Abstract

Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

What is claimed is: 
     
       1. A method of fabricating a nanosheet semiconductor device, the method comprising:
 providing a structure comprising: 
 a vertical stack of alternating channel layers and sacrificial layers, wherein the vertical stack extends horizontally in a first direction; 
 a dummy gate disposed over the vertical stack, wherein the dummy gate extends horizontally in a second direction perpendicular to the first direction; 
 first inner spacers disposed at opposite ends of the sacrificial layers in the first direction; 
 forming first and second source/drain regions contacting opposite ends of the channel layers and the first inner spacers in the first direction; 
 subsequent to forming the first and second source/drain regions, reducing a width of the dummy gate in the first direction; and 
 subsequent to reducing the width of the dummy gate, depositing a dielectric layer over the dummy gate and portions of the source/drain regions. 
 
     
     
       2. The method of  claim 1 , wherein the width of the dummy gate is reduced such that the dummy gate is not disposed over the source/drain regions. 
     
     
       3. The method of  claim 1 , wherein:
 the vertical stack is disposed on a substrate; and 
 the width of the dummy gate is reduced such that the dummy gate is disposed between opposing vertical lines extending perpendicular to the substrate; and 
 the opposing vertical lines extend through the first inner spacers. 
 
     
     
       4. The method of  claim 1 , reducing the width of the dummy gate comprises etching ends of the dummy gate. 
     
     
       5. The method of  claim 1 , further comprising: subsequent to reducing the width of the dummy gate, removing the first inner spacers to form spaces between the sacrificial layers and the source/drain regions. 
     
     
       6. The method of  claim 5 , wherein: the dielectric layer further forms second inner spacers in the spaces formed by removing the first inner spacers. 
     
     
       7. The method of  claim 5 , wherein removing the first inner spacers comprises a hydrofluoric, HF, acid solution. 
     
     
       8. The method of  claim 1 , wherein a lateral width of the channel layers is greater than a lateral width of the sacrificial layers. 
     
     
       9. The method of  claim 1 , further comprising:
 prior to reducing the width of the dummy gate, etching exposed portions of the vertical stack, using the dummy gate as a mask, to form a nanosheet fin comprising remaining portions of the channel layers and remaining portions of the sacrificial layers. 
 
     
     
       10. The method of  claim 9 , wherein etching exposed portions of the vertical stack comprises: reducing a width of the channel layers in the first direction. 
     
     
       11. The method of  claim 10 , wherein reducing the width of the channel layers comprises:
 oxidizing the ends of the channel layers; and 
 etching the oxidized ends of the channel layers. 
 
     
     
       12. The method of  claim 9 , wherein etching exposed portions of the vertical stack comprises: reducing a width of the sacrificial layers in the first direction. 
     
     
       13. The method of  claim 12 , wherein reducing the width of the sacrificial layers comprises:
 oxidizing ends of the sacrificial layers; and 
 etching the oxidized ends of the sacrificial layers. 
 
     
     
       14. The method of  claim 1 , wherein the sacrificial layers comprise Si and Ge. 
     
     
       15. The method of  claim 1 , wherein the channel layers comprise Si. 
     
     
       16. The method of  claim 1 , further comprising:
 depositing an interlevel dielectric, ILD, layer over the dielectric layer. 
 
     
     
       17. The method of  claim 16 , further comprising:
 planarizing the ILD layer. 
 
     
     
       18. The method of  claim 16 , wherein the ILD layer comprises an oxide and/or a borophosphosilicate glass. 
     
     
       19. The method of  claim 1 , wherein the dielectric layer comprises carbon. 
     
     
       20. The method of  claim 1 , wherein the first inner spacers comprise an oxide.