Inventor

SPORRE JOHN R

US86 patents

⚠️ This page may combine multiple inventors who share the name “SPORRE JOHN R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SPORRE JOHN R

IBM

Nanosheet channel-to-source and drain isolation

Air gap spacer for metal gates

Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

Fin cut during replacement gate formation

Cutting fins and gates in CMOS devices

Single spacer for complementary metal oxide semiconductor process flow

Method to form dual channel semiconductor material fins

Sub-lithographic magnetic tunnel junctions for magnetic random access memory devices

Method and structure for enabling high aspect ratio sacrificial gates

Nanosheet channel-to-source and drain isolation

Nanosheet channel-to-source and drain isolation

Fin cut during replacement gate formation

Fin patterns with varying spacing without fin cut

Forming stacked nanowire semiconductor device

Air gap spacer for metal gates

Vertical transport field effect transistor with precise gate length definition

Gate height control and ILD protection

Method and structure for enabling high aspect ratio sacrificial gates

Method to form dual channel semiconductor material fins

Dummy gate formation using spacer pull down hardmask

Method and structure for enabling high aspect ratio sacrificial gates

FinFET gate cut after dummy gate removal

Removal of trilayer resist without damage to underlying structure

Super long channel device within VFET architecture

Sub-lithographic magnetic tunnel junctions for magnetic random access memory devices

Gate cut device fabrication with extended height gates

Method and structure for enabling high aspect ratio sacrificial gates

Fin cut to prevent replacement gate collapse on STI

Air gap spacer for metal gates

Gate cut device fabrication with extended height gates

Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

Gate cut on a vertical field effect transistor with a defined-width inorganic mask

Fin cut during replacement gate formation

Fin patterns with varying spacing without fin cut

Margin for fin cut using self-aligned triple patterning

Fin patterns with varying spacing without fin cut

Fin patterns with varying spacing without fin cut

Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

Dummy gate formation using spacer pull down hardmask

Gate cut on a vertical field effect transistor with a defined-width inorganic mask

Method and structure to enable dual channel fin critical dimension control

Single spacer for complementary metal oxide semiconductor process flow

Stress retention in fins of fin field-effect transistors

Gate cutting for a vertical transistor device

TESSERA INC

Nanosheet channel-to-source and drain isolation

Air gap spacer for metal gates

TESSERA LLC

Nanosheet channel-to-source and drain isolation

Air gap spacer for metal gates

ADEIA SEMICONDUCTOR SOLUTIONS LLC

FinFET gate cut after dummy gate removal

GLOBALFOUNDRIES INC

Gate cut in replacement metal gate process