Inventor

THOMAS TESSIL

IN51 patents

⚠️ This page may combine multiple inventors who share the name “THOMAS TESSIL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

THOMAS TESSIL

INTEL CORP

Memory channel that supports near memory and far memory access

Speculatively performing read transactions

Memory agent with error hardware

Memory channel that supports near memory and far memory access

Memory channel that supports near memory and far memory access

Method and apparatus for scrubbing memory

Memory channel that supports near memory and far memory access

Booting with sub socket partitioning

Reducing power consumption of uncore circuitry of a processor

Mechanism for read-only memory built-in self-test

Memory channel that supports near memory and far memory access

Apparatus and method for thermal management in a multi-chip package

Opportunistic transmission of software state information within a link based computing system

Apparatus and method to provide a thermal parameter report for a multi-chip package

Apparatus and method to provide a thermal parameter report for a multi-chip package

Rank-specific cyclic redundancy check

Opportunistic transmission of computing system state information within a link based computing system

Controlling average power limits of a processor

Controlling average power limits of a processor

Method, system and apparatus for handling events for partitions in a socket with sub-socket partitioning

Reducing power consumption of uncore circuitry of a processor

Processor having frequency of operation information for guaranteed operation under high temperature events

Method, system and apparatus for main memory access subsystem usage to different partitions in a socket with sub-socket partitioning

Methods and apparatus to effect hot reset for an on die non-root port integrated device

Generating and communicating platform event digests from a processor of a system

Apparatus and method for reducing leakage power of a circuit

Apparatus and method for reducing leakage power of a circuit

Capability determination for computing resource allocation

ADVANCED RISC MACH LTD

Cache power management

Apparatus and method for handling address decoding in a system-on-chip

System architecture with query based address translation for access validation

Delegating component power control

PCIe communications

Message protocol for a data processing system

PCIe routing

Data processing circuitry and apparatus for packet-based data communications

Peripheral component handling of memory read requests

Apparatus and method for processing flush requests within a packet network

Responding to unresponsive processing circuitry

Secure memory translations

HARIKUMAR AJAY

Method, system and apparatus for handling events for partitions in a socket with sub-socket partitioning

Method, apparatus, and system for shared cache usage to different partitions in a socket with sub-socket partitioning

Method, system and apparatus for memory address mapping for sub-socket partitioning

NALE BILL

Memory channel that supports near memory and far memory access

BALASUBRAMANIAN SRIKANTH

Reducing power consumption of uncore circuitry of a processor

THOMAS TESSIL

Idle power reduction for memory subsystems

NATU MAHESH S

Monitoring resource usage by a virtual machine

SUBASHCHANDRABOSE RAMESH

Rank-specific cyclic redundancy check

GANESAN BASKARAN

Memory link power management

MURTY KESHAVRAM N

Opportunistic transmission of software state information within a link based computing system