Methods and apparatus to effect hot reset for an on die non-root port integrated device

Abstract

In an embodiment, a processor includes at least one core to initiate a hot reset, and a peripheral device that is coupled to a root complex fabric via through the root port via an peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge. The processor also includes a power control unit that includes reset logic to decouple the peripheral device from the root complex fabric responsive to initiation of the hot reset. After the peripheral device is decoupled from the root complex fabric, the reset logic is to assert a reset of the peripheral device while a first core of the at least one core is in operation. Other embodiments are described and claimed.

What is claimed is: 
     
       1. A processor comprising:
 an on-chip peripheral device; 
 at least one core to provide an indication to initiate a hot reset, the hot reset comprising a reset of the on-chip peripheral device without shut-down of the at least one core; 
 a root complex fabric; 
 a peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge to couple the on-chip peripheral device to the root complex fabric; and 
 a power control unit including reset logic to, responsive to the indication to initiate the hot reset:
 quiesce the on-chip peripheral device; 
 quiesce the PCIE to OSF bridge to decouple the on-chip peripheral device from the root complex fabric; and 
 in response to a determination that the on-chip peripheral device and the PCIE to OSF bridge are quiesced, cause a reset of the PCIE to OSF bridge and the reset of the on-chip peripheral device while a first core of the at least one core is in operation. 
 
 
     
     
       2. The processor of  claim 1 , wherein the reset logic is to provide an indication of an impending hot reset to a root port of the root complex fabric. 
     
     
       3. The processor of  claim 2 , wherein responsive to receipt by the root port of the indication of the impending hot reset, the PCIE to OSF bridge is to refrain from granting credits for outbound transactions toward the root port that are received from the on-chip peripheral device. 
     
     
       4. The processor of  claim 1 , wherein the reset logic is to save power management contents of a first register of the on-chip peripheral device into storage of the power control unit prior to decoupling the on-chip peripheral device from the root complex fabric. 
     
     
       5. The processor of  claim 1 , wherein the reset logic is to quiesce the PCIE to OSF bridge by setting a configuration register of the PCIE to OSF bridge. 
     
     
       6. The processor of  claim 1 , wherein the reset logic is to quiesce the on-chip peripheral device by providing to the on-chip peripheral device a reset warn command, wherein on receipt of the reset warn command the on-chip peripheral device is to drop a posted write request that is received. 
     
     
       7. The processor of  claim 1 , wherein the reset logic is to quiesce the on-chip peripheral device by providing to the on-chip peripheral device a reset warn command, wherein upon receipt of the reset warn command the on-chip peripheral device is to respond to a read request with a response that indicates that the read request is unsupported. 
     
     
       8. The processor of  claim 1 , wherein the reset logic is to quiesce the on-chip peripheral device by providing to the on-chip peripheral device a reset warn command, wherein upon receipt of the reset warn command the on-chip peripheral device is to drop at least one incoming message responsive to receipt of the at least one incoming message. 
     
     
       9. The processor of  claim 1 , wherein the reset logic is to quiesce the on-chip peripheral device by sending to the on-chip peripheral device a reset warn command, and responsive to receipt of the reset warn command and completion of pending transactions, the on-chip peripheral device is to indicate to the reset logic that the on-chip peripheral device is in a quiescent state. 
     
     
       10. The processor of  claim 1 , wherein the on-chip peripheral device includes a sideband interface to couple to a sideband bus and the reset logic is to decouple the on-chip peripheral device from the sideband bus responsive to initiation of the hot reset. 
     
     
       11. The processor of  claim 1 , wherein the reset logic is to cause the reset of the on-chip peripheral device and the reset of the PCIE to OSF bridge by asserting a primary domain reset to the on-chip peripheral device and the PCIE to OSF bridge, wherein the primary domain reset resets all logic clocked by a primary clock. 
     
     
       12. A system on a chip (SOC) comprising:
 an on-chip peripheral device; 
 at least one core including a first core to provide an indication to initiate a reset of the on-chip peripheral device without shut-down of the at least one core; 
 a root complex fabric; 
 a peripheral component interconnect express (PCIE) to on-chip system fabric (OSF) bridge coupling the on-chip peripheral device to the root complex fabric; and 
 reset logic to, responsive to the indication to initiate the reset of the on-chip peripheral device:
 quiesce the on-chip peripheral device; 
 quiesce the PCIE to OSF bridge to decouple the on-chip peripheral device from the root complex fabric; and 
 in response to a determination that the on-chip peripheral device and the PCIE to OSF bridge are quiesced, cause a reset of the PCIE to OSF bridge and the reset of the on-chip peripheral device while the first core is in operation. 
 
 
     
     
       13. The SOC of  claim 12 , wherein the reset logic is to quiesce the on-chip peripheral device by sending a reset warn command to the on-chip peripheral device. 
     
     
       14. The SOC of  claim 13 , wherein the reset logic is to quiesce the PCIE to OSF bridge by setting a configuration register of the PCIE to OSF bridge. 
     
     
       15. The SOC of  claim 12 , wherein the reset logic is to cause the reset of the on-chip peripheral device and the reset of the PCIE to OSF bridge by asserting a primary domain reset to the on-chip peripheral device and the PCIE to OSF bridge, wherein the primary domain reset resets all logic clocked by a primary clock. 
     
     
       16. A non-transitory computer-readable medium storing instructions that, in response to being executed on a computing device, cause the computing device to:
 in response to an indication to initiate a reset of an on-chip peripheral device without shut-down of an entire system on a chip (SOC) that includes the on-chip peripheral device:
 quiesce the on-chip peripheral device; 
 quiesce a PCIE to OSF bridge included in the SOC, the PCIE to OSF bridge to couple the on-chip peripheral device to a root complex fabric included in the SOC; and 
 in response to a determination that the on-chip peripheral device and the PCIE to OSF bridge are quiesced, cause a reset of the PCIE to OSF bridge and the reset of the peripheral device while at least one core of the SoC is in operation. 
 
 
     
     
       17. The computer-readable medium of  claim 16 , further including instructions to cause the reset of the on-chip peripheral device and the reset of the PCIE to OSF bridge by asserting a primary domain reset to the on-chip peripheral device and the PCIE to OSF bridge, wherein the primary domain reset resets all logic clocked by a primary clock. 
     
     
       18. The computer-readable medium of  claim 16 , wherein the PCIE to OSF bridge is to convert data between a PCIE protocol and an OSF protocol. 
     
     
       19. The computer-readable medium of  claim 18 , further comprising instructions to quiesce the on-chip peripheral device by sending a reset warn command to the on-chip peripheral device. 
     
     
       20. The computer-readable medium of  claim 16 , further comprising instructions to quiesce the PCIE to OSF bridge by setting a configuration register of the PCIE to OSF bridge.