Inventor

SAETOW ANUWAT

US37 patents

⚠️ This page may combine multiple inventors who share the name “SAETOW ANUWAT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAETOW ANUWAT

IBM

Implementing ECC redundancy using reconfigurable logic blocks

Self monitoring and self repairing ECC

Volatile and non-volatile memory in a TSV module

Mitigation of EMI/ESD-caused transmission errors on an electronic circuit

Implementing signal integrity fail recovery and mainline calibration for DRAM

Implementing dynamic SEU detection and correction method and circuit

Granular variable impedance tuning

Implementing SEU detection method and circuit

Implementing enhanced reliability of systems utilizing dual port DRAM

Reference voltage modification in a memory device

Hardware abstraction in software or firmware for hardware calibration

Real-time error debugging

Mitigation of side effects of simultaneous switching of input/output (I/O data signals

SRAM bitline equalization using phase change material

SRAM bitline equalization using phase change material

Handling repaired memory array elements in a memory of a computer system

Voltage rail monitoring to detect electromigration

Voltage rail monitoring to detect electromigration

Self monitoring and self repairing ECC

Prioritizing refreshes in a memory device

Reference voltage modification in a memory device

Prioritizing refreshes in a memory device

Managing heterogeneous memory resource within a computing system

Auto-disabling DRAM error checking on threshold

Auto-disabling DRAM error checking on threshold

Implementing enhanced reliability of systems utilizing dual port DRAM

Implementing simultaneous read and write operations utilizing dual port DRAM

Implementing simultaneous read and write operations utilizing dual port DRAM

Coherency management for volatile and non-volatile memory in a through-silicon via (TSV) module

Memory device command-address-control calibration

System and memory controller for interruptible memory refresh

Memory device for interruptible memory refresh

Determining timeout values for computing systems

Correcting a data storage error caused by a broken conductor using bit inversion

CORDERO EDGAR R

Implementing chip to chip calibration within a TSV stack

Implementing enhanced hardware assisted DRAM repair using a data register for DRAM repair selectively provided in a DRAM module

Implementing DRAM command timing adjustments to alleviate DRAM failures