Inventor
BUSCH ROBERT E
US23 patents
Patents
23 patentsUS4807195AFeb 21, 1989
Apparatus and method for providing a dual sense amplifier with divided bit line isolation
IBM161 citations98
US6430073B1Aug 6, 2002
Dram CAM cell with hidden refresh
IBM95 citations97
US5530836AJun 25, 1996
Method and apparatus for multiple memory bank selection
IBM83 citations96
US6208572B1Mar 27, 2001
Semiconductor memory device having resistive bitline contact testing
IBM75 citations94
US6760881B2Jul 6, 2004
Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM)
IBM30 citations92
US6487101B1Nov 26, 2002
Use of search lines as global bitlines in a cam design
IBM24 citations92
US6201750B1Mar 13, 2001
Scannable fuse latches
IBM28 citations92
US4992984AFeb 12, 1991
Memory module utilizing partially defective memory chips
IBM44 citations92
US6687144B2Feb 3, 2004
High reliability content-addressable memory using shadow content-addressable memory
IBM27 citations91
US5276846AJan 4, 1994
Fast access memory structure
IBM27 citations91
US5036495AJul 30, 1991
Multiple mode-set for IC chip
IBM22 citations91
US7120732B2Oct 10, 2006
Content addressable memory structure
IBM12 citations84
US6501675B2Dec 31, 2002
Alternating reference wordline scheme for fast DRAM
IBM8 citations74
US5633605AMay 27, 1997
Dynamic bus with singular central precharge
IBM10 citations74
US6791855B2Sep 14, 2004
Redundant array architecture for word replacement in CAM
IBM11 citations73
US6728123B2Apr 27, 2004
Redundant array architecture for word replacement in CAM
IBM8 citations73
US6650561B2Nov 18, 2003
High reliability content-addressable memory using shadow content-addressable memory
IBM7 citations72
US6442055B1Aug 27, 2002
System and method for conserving power in a content addressable memory by providing an independent search line voltage
IBM3 citations63
US7117400B2Oct 3, 2006
Memory device with data line steering and bitline redundancy
IBM5 citations62
US6760240B2Jul 6, 2004
CAM cell with interdigitated search and bit lines
IBM3 citations62
US6941435B2Sep 6, 2005
Integrated circuit having register configuration sets
IBM2 citations60
US7337268B2Feb 26, 2008
Content addressable memory structure
IBM0 citations52
US7464217B2Dec 9, 2008
Design structure for content addressable memory
IBM1 citations51