Inventor · disambiguated record
Jonathan Lachman
Also filed as: LACHMAN JONATHAN · LACHMAN JONATHAN E
14 granted patents·4 pending applications·121 citations·filing 1997–2020
91Inventor score
Files withHEWLETT PACKARD DEVELOPMENT CO7HEWLETT PACKARD CO4CYPRESS SEMICONDUCTOR CORP2LACHMAN JONATHAN E1UTMC MICROELECTRONIC SYSTEMS I1
Top patents by PatentIndex Score
18 records- 0180US6271568B1Voltage controlled resistance modulation for single event upset immunityUTMC MICROELECTRONIC SYSTEMS I·Filed 1997·Granted Aug 7, 2001·52 cites·38 claims
- 0263US6931607B2System and method for designing circuits in a SOI processHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Aug 16, 2005·11 cites·12 claims
- 0363US6275442B1Address decoder and method for ITS accelerated stress testingHEWLETT PACKARD CO·Filed 2000·Granted Aug 14, 2001·15 cites·18 claims
- 0462US6314039B1Characterization of sense amplifiersHEWLETT PACKARD CO·Filed 2000·Granted Nov 6, 2001·12 cites·20 claims
- 0559US10978127B2Ferroelectric random access memory sensing schemeCYPRESS SEMICONDUCTOR CORP·Filed 2020·Granted Apr 13, 2021·0 cites·18 claims
- 0659US6549060B1Dynamic logic MUXHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Apr 15, 2003·11 cites·20 claims
- 0758US6380779B1Edge-triggered, self-resetting pulse generatorHEWLETT PACKARD CO·Filed 2001·Granted Apr 30, 2002·8 cites·22 claims
- 0847US10586583B2Ferroelectric random access memory sensing schemeCYPRESS SEMICONDUCTOR CORP·Filed 2018·Granted Mar 10, 2020·0 cites·19 claims
- 0947US6836871B2Process and system for developing dynamic circuit guidelinesHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Dec 28, 2004·1 cites·30 claims
- 1046US6775812B2Layout design process and system for providing bypass capacitance and compliant density in an integrated circuitHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Aug 10, 2004·6 cites·34 claims
- 1139US6940778B2System and method for reducing leakage in memory cells using wordline controlHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Sep 6, 2005·2 cites·10 claims
- 1238US6944807B2Method and apparatus for achieving higher product yields by using fractional portions of imbedded memory arraysHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Sep 13, 2005·2 cites·5 claims
- 1336US6301140B1Content addressable memory cell with a bootstrap improved compareHEWLETT PACKARD CO·Filed 2000·Granted Oct 9, 2001·1 cites·4 claims
- 1432US6580635B1Bitline splitterHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jun 17, 2003·0 cites·10 claims
- 1530US2003026135A1Data-shifting scheme for utilizing multiple redundant elementsFiled 2001·Application pending·0 cites
- 1630US2003042933A1Detection of errors in dynamic circuitsFiled 2001·Application pending·0 cites
- 1729US2007081409A1Reduced bitline leakage currentWUU JOHN J·Filed 2005·Application pending·0 cites
- 1826US2006133135A1Reducing power in SRAMs while maintaining cell stabilityLACHMAN JONATHAN E·Filed 2004·Application pending·0 cites
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