Inventor

WEN MING-CHANG

TW38 patents

⚠️ This page may combine multiple inventors who share the name “WEN MING-CHANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WEN MING-CHANG

TAIWAN SEMICONDUCTOR MFG CO LTD

Cut metal gate process for reducing transistor spacing

Dielectric spacer to prevent contacting shorting

Dielectric spacer to prevent contacting shorting

Etch stop layer between substrate and isolation structure

Structure for fringing capacitance control

Local gate height tuning by cmp and dummy gate design

Local gate height tuning by CMP and dummy gate design

Semiconductor device having nanosheet transistor and methods of fabrication thereof

Semiconductor device having a metal gate and formation method thereof

SRAM structure and method for forming the same

Semiconductor device having isolation structure formed of low-k dielectric material and method for forming the same

Cut metal gate process for reducing transistor spacing

Dielectric spacer to prevent contacting shorting

Etch stop layer between substrate and isolation structure

Cut metal gate process for reducing transistor spacing

Cut metal gate process for reducing transistor spacing

Structure and method for alignment marks

Etch stop layer between substrate and isolation structure

Semiconductor device having cut gate dielectric

Semiconductor device transistor having multiple channels with different widths and materials

Local gate height tuning by CMP and dummy gate design

Structure for fringing capacitance control

Semiconductor device having nanosheet transistor and methods of fabrication thereof

Semiconductor device having cut gate dielectric

Method for forming semiconductor device

Creating devices with multiple threshold voltages by cut-metal-gate process

Creating devices with multiple threshold voltage by cut-metal-gate process

SRAM structure and method for forming the same

Profile control of a gap fill structure

Profile control of a gap fill structure

Structure and method for alignment marks

Cut metal gate process for reducing transistor spacing

Structure and method for overlay marks

WANG HSIEN-CHENG

Cross quadrupole double lithography method and apparatus for semiconductor device fabrication using two apertures

Structure and method for overlay marks

WEN MING-CHANG

Structure and method for alignment marks

IND TECH RES INST

Process for preparing nanofluids with rotating packed bed reactor

TAIWAN SEMICONDUCTOR MFG

Cross quadrupole double lithography method using two complementary apertures