Semiconductor device having nanosheet transistor and methods of fabrication thereof

Abstract

Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.

The invention claimed is: 
     
       1. A method for forming a semiconductor device structure, comprising:
 forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged; 
 forming a sacrificial gate structure over a portion of the fin structure; 
 removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure; 
 forming an epitaxial source/drain feature in the source/drain region; 
 removing portions of the sacrificial gate structure to expose the first and second semiconductor layers; 
 removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers; 
 after removing portions of the second semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers in the same process, wherein at least a portion of the conformal gate dielectric layer is disposed between adjacent first semiconductor layers; and 
 forming a gate electrode layer on the conformal gate dielectric layer. 
 
     
     
       2. The method of  claim 1 , wherein portions of the second semiconductor layers are removed so that a height of each second semiconductor layer is greater than the width of each second semiconductor layer. 
     
     
       3. The method of  claim 2 , wherein the conformal gate dielectric layer is formed to surround four surfaces of at least one first semiconductor layer. 
     
     
       4. The method of  claim 1 , wherein portions of the second semiconductor layers are removed so that the width of each second semiconductor layer is less than the width of each of the first semiconductor layers. 
     
     
       5. The method of  claim 1 , wherein the second semiconductor layers comprise SiGe, and each of the second semiconductor layers has similar or identical germanium atomic percentage. 
     
     
       6. The method of  claim 5 , wherein each of the second semiconductor layers has an atomic percentage of germanium in a range between about 5 at. % and about 25 at. %. 
     
     
       7. The method of  claim 1 , further comprising:
 after removing portions of the sacrificial gate structure, implanting dopants into the second semiconductor layers. 
 
     
     
       8. The method of  claim 7 , wherein the dopants are implanted so that the second semiconductor layers at an upper region of the stack of the semiconductor layers has a dopant concentration greater than a dopant concentration of the second semiconductor layers at a middle region of the stack of the semiconductor layers. 
     
     
       9. The method of  claim 7 , wherein the second semiconductor layers at an upper region of the stack of the semiconductor layers has a first width and the second semiconductor layers at a lower region of the stack of the semiconductor layers has a second width less than the first width. 
     
     
       10. A method for forming a semiconductor device structure, comprising:
 forming a sacrificial gate structure over a portion of a fin structure having a stack of semiconductor layers, wherein the stack of semiconductor layers comprises silicon-containing layers and germanium-containing layers alternatingly arranged, and at least some germanium-containing layers of the stack of the semiconductor layers have a first germanium atomic percentage, and at least some germanium-containing layers of the stack of the semiconductor layers have a second germanium atomic percentage greater than the first germanium atomic percentage; 
 removing the silicon-containing layers and the germanium-containing layers not covered by the sacrificial gate structure; 
 forming an epitaxial source/drain feature in regions where the silicon-containing layers and the germanium-containing layers were removed; 
 removing portions of the sacrificial gate structure to expose the silicon-containing layers and the germanium-containing layers; 
 selectively removing portions of the germanium-containing layers so that at least one germanium-containing layer remaining between two adjacent silicon-containing layers has a height and the two adjacent silicon-containing layers have a width that is greater than the height; and 
 forming a gate electrode layer over exposed surfaces of the silicon-containing layers and the germanium-containing layers. 
 
     
     
       11. The method of  claim 10 , wherein the gate electrode layer is formed to fully surround at least one silicon-containing layer. 
     
     
       12. The method of  claim 10 , wherein the at least one germanium-containing layer between two adjacent silicon-containing layers comprises:
 a first portion in contact with a first silicon-containing layer; 
 a second portion in contact with a second silicon-containing layer; and 
 a third portion disposed between the first and second portion, wherein the third portion has a width less than a width of the first and second portions. 
 
     
     
       13. The method of  claim 10 , wherein at least one germanium-containing layer between two adjacent silicon-containing layers has a width that is less than the height of the silicon-containing layer. 
     
     
       14. A method for forming a semiconductor device structure, comprising:
 forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged; 
 forming a sacrificial gate structure over a portion of the fin structure; 
 removing the first and second semiconductor layers not covered by the sacrificial gate structure; 
 forming an epitaxial source/drain feature in the source/drain region; 
 removing portions of the sacrificial gate structure to expose the first and second semiconductor layers; and 
 selectively removing portions of the second semiconductor layers so that at least one second semiconductor layer remains between two adjacent first semiconductor layers, and the at least one second semiconductor layer has a height and a width that is less than the height. 
 
     
     
       15. The method of  claim 14 , wherein the second semiconductor layers at an upper region of the stack of the semiconductor layers has a first germanium atomic percentage, and the second semiconductor layers at a lower region of the stack of the semiconductor layers has a second germanium atomic percentage greater than the first germanium atomic percentage. 
     
     
       16. The method of  claim 15 , wherein the second semiconductor layers at a middle region of the stack of the semiconductor layers has a third germanium atomic percentage similar or identical to the first germanium atomic percentage. 
     
     
       17. The method of  claim 15 , wherein the second semiconductor layers at the upper region of the stack of the semiconductor layers has a first width and the second semiconductor layers at the lower region of the stack of the semiconductor layers has a second width less than the first width. 
     
     
       18. The method of  claim 14 , wherein the at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers. 
     
     
       19. The method of  claim 14 , further comprising:
 after removing portions of the sacrificial gate structure, implanting dopants into the second semiconductor layers. 
 
     
     
       20. The method of  claim 19 , wherein the dopants comprise boron (B), phosphorus (P), germanium (Ge), arsenic (As), selenium (Se), bromine (Br), krypton (Kr), silicon (Si), sulfur (S), chlorine (Cl), argon (Ar), or gallium (Ga), or the like, or any combination thereof.