Inventor
LANZILLO NICHOLAS ANTHONY
US101 patents
Patents
50 patentsUS11195993B2Dec 7, 2021
Encapsulation topography-assisted self-aligned MRAM top contact
IBM7 citations84
US11152257B2Oct 19, 2021
Barrier-less prefilled via formation
IBM5 citations84
US11756887B2Sep 12, 2023
Backside floating metal for increased capacitance
IBM5 citations75
US11894265B2Feb 6, 2024
Top via with damascene line and via
IBM2 citations73
US11276639B2Mar 15, 2022
Conductive lines with subtractive cuts
IBM3 citations73
US11195795B1Dec 7, 2021
Well-controlled edge-to-edge spacing between adjacent interconnects
IBM3 citations73
US11195792B2Dec 7, 2021
Top via stack
IBM2 citations73
US11189568B2Nov 30, 2021
Top via interconnect having a line with a reduced bottom dimension
IBM2 citations73
US11171084B2Nov 9, 2021
Top via with next level line selective growth
IBM2 citations73
US11139201B2Oct 5, 2021
Top via with hybrid metallization
IBM2 citations73
US10978343B2Apr 13, 2021
Interconnect structure having fully aligned vias
IBM2 citations73
US10727124B2Jul 28, 2020
Structure and method for forming fully-aligned trench with an up-via integration scheme
IBM3 citations73
US12148682B2Nov 19, 2024
Memory cell in wafer backside
IBM2 citations72
US11908791B2Feb 20, 2024
Partial subtractive supervia enabling hyper-scaling
IBM2 citations72
US12538553B2Jan 27, 2026
Contact structure for power delivery on semiconductor device
IBM1 citations64
US12424549B2Sep 23, 2025
Skip-level TSV with hybrid dielectric scheme for backside power delivery
IBM1 citations64
US12588487B2Mar 24, 2026
Tight pitch directional selective via growth
IBM0 citations63
US12557328B2Feb 17, 2026
Vertical-transport field-effect transistor with backside source/drain connections
IBM0 citations63
US12550704B2Feb 10, 2026
Subtractive skip via
IBM0 citations63
US12550719B2Feb 10, 2026
VTFET circuit with optimized output
IBM0 citations63
US12550713B2Feb 10, 2026
Hybrid buried power rail structure with dual front side and backside processing
IBM0 citations63
US12525529B2Jan 13, 2026
Forming line end vias
IBM0 citations63
US12506080B2Dec 23, 2025
Reduced capacitance between power via bar and gates
IBM0 citations63
US12494428B2Dec 9, 2025
Airgap spacer for power via
IBM0 citations63
US12484248B2Nov 25, 2025
Source/drain contact at tight cell boundary
IBM0 citations63
US12463132B2Nov 4, 2025
Semiconductor structure with backside metallization layers
IBM0 citations63
US12463130B2Nov 4, 2025
Wrap around metal via structure
IBM0 citations63
US12463128B2Nov 4, 2025
Interconnect structures with vias having vertical and horizontal sections
IBM0 citations63
US12457793B2Oct 28, 2025
Vertical transport field effect transistor (VTFET) with backside wraparound contact
IBM0 citations63
US12439608B2Oct 7, 2025
MRAM integration with self-aligned direct back side contact
IBM0 citations63
US12424557B2Sep 23, 2025
Dual structured buried rail
IBM0 citations63
US12417963B2Sep 16, 2025
Isolation rail between backside power rails
IBM0 citations63
US12417979B2Sep 16, 2025
Pass-through wiring in notched interconnect
IBM0 citations63
US12412836B2Sep 9, 2025
Backside power plane
IBM0 citations63
US12400960B2Aug 26, 2025
Vertical-transport field-effect transistor with backside gate contact
IBM0 citations63
US12334442B2Jun 17, 2025
Dielectric caps for power and signal line routing
IBM0 citations63
US12261056B2Mar 25, 2025
Top via patterning using metal as hard mask and via conductor
IBM0 citations63
US12243819B2Mar 4, 2025
Single-mask alternating line deposition
IBM0 citations63
US12142525B2Nov 12, 2024
Self-aligning spacer tight pitch via
IBM0 citations63
US11990410B2May 21, 2024
Top via interconnect having a line with a reduced bottom dimension
IBM0 citations63
US11961759B2Apr 16, 2024
Interconnects having spacers for improved top via critical dimension and overlay tolerance
IBM0 citations63
US11908738B2Feb 20, 2024
Interconnect including integrally formed capacitor
IBM0 citations63
US11842961B2Dec 12, 2023
Advanced metal interconnects with a replacement metal
IBM0 citations63
US11823998B2Nov 21, 2023
Top via with next level line selective growth
IBM0 citations63
US11804406B2Oct 31, 2023
Top via cut fill process for line extension reduction
IBM0 citations63
US11791258B2Oct 17, 2023
Conductive lines with subtractive cuts
IBM0 citations63
US11670542B2Jun 6, 2023
Stepped top via for via resistance reduction
IBM0 citations63
US11621189B2Apr 4, 2023
Barrier-less prefilled via formation
IBM0 citations63
US11600565B2Mar 7, 2023
Top via stack
IBM0 citations63
US11437317B2Sep 6, 2022
Single-mask alternating line deposition
IBM0 citations63
Showing the top 50 of 101 patents by PatentIndex Score.