Inventor · disambiguated record
Thomas R. Wik
Also filed as: WIK THOMAS R · WIK THOMAS ROBERT
24 granted patents·1 pending application·880 citations·filing 1994–2014
97Inventor score
Files withLSI LOGIC CORP15WIK THOMAS ROBERT3ESILICON CORP2ADAPTIVE DESIGN SOLUTIONS INC1AT & T CORP1
Top patents by PatentIndex Score
25 records- 0196US5784328AMemory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM arrayLSI LOGIC CORP·Filed 1996·Granted Jul 21, 1998·209 cites·18 claims
- 0294US5982659AMemory cell capable of storing more than two logic states by using different via resistancesLSI LOGIC CORP·Filed 1996·Granted Nov 9, 1999·128 cites·19 claims
- 0392US5987632AMethod of testing memory operations employing self-repair circuitry and permanently disabling memory locationsLSI LOGIC CORP·Filed 1997·Granted Nov 16, 1999·106 cites·19 claims
- 0491US5559463ALow power clock circuitLUCENT TECHNOLOGIES INC·Filed 1994·Granted Sep 24, 1996·61 cites·5 claims
- 0590US5796650AMemory circuit including write control unit wherein subthreshold leakage may be reducedLSI LOGIC CORP·Filed 1997·Granted Aug 18, 1998·107 cites·20 claims
- 0684US9762261B2Error detection and correction in ternary content addressable memory (TCAM)ESILICON CORP·Filed 2014·Granted Sep 12, 2017·8 cites·18 claims
- 0781US7746921B1Resonant digital data transmissionWIK THOMAS ROBERT·Filed 2006·Granted Jun 29, 2010·12 cites·11 claims
- 0877US9780722B1Low-cost efficient solar panelsWIK THOMAS ROBERT·Filed 2007·Granted Oct 3, 2017·4 cites·6 claims
- 0976US5808932AMemory system which enables storage and retrieval of more than two states in a memory cellLSI LOGIC CORP·Filed 1996·Granted Sep 15, 1998·39 cites·18 claims
- 1075US6370078B1Way to compensate the effect of coupling between bitlines in a multi-port memoriesLSI LOGIC CORP·Filed 2000·Granted Apr 9, 2002·22 cites·29 claims
- 1174US6233197B1Multi-port semiconductor memory and compiler having capacitance compensationLSI LOGIC CORP·Filed 2000·Granted May 15, 2001·21 cites·11 claims
- 1274US5761110AMemory cell capable of storing more than two logic states by using programmable resistancesLSI LOGIC CORP·Filed 1996·Granted Jun 2, 1998·34 cites·20 claims
- 1372US6507524B1Integrated circuit memory having column redundancyLSI LOGIC CORP·Filed 2000·Granted Jan 14, 2003·19 cites·17 claims
- 1469US8921680B1Low-cost solar collectorWIK THOMAS ROBERT·Filed 2007·Granted Dec 30, 2014·2 cites·15 claims
- 1566US5867423AMemory circuit and method for multivalued logic storage by process variationsLSI LOGIC CORP·Filed 1997·Granted Feb 2, 1999·25 cites·22 claims
- 1662US6137716AMemory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cellLSI LOGIC CORP·Filed 1997·Granted Oct 24, 2000·18 cites·10 claims
- 1761US7557618B1Conditioning logic technologyWIK THOMAS R·Filed 2007·Granted Jul 7, 2009·5 cites·10 claims
- 1859US7603509B1Crossbar switch with grouped inputs and outputsADAPTIVE DESIGN SOLUTIONS INC·Filed 2008·Granted Oct 13, 2009·3 cites·3 claims
- 1959US5847990ARam cell capable of storing 3 logic statesLSI LOGIC CORP·Filed 1996·Granted Dec 8, 1998·19 cites·5 claims
- 2054US9529669B2Error detection and correction in binary content addressable memory (BCAM)ESILICON CORP·Filed 2014·Granted Dec 27, 2016·0 cites·19 claims
- 2151US5841695AMemory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cellLSI LOGIC CORP·Filed 1997·Granted Nov 24, 1998·11 cites·20 claims
- 2248US5506519ALow energy differential logic gate circuitry having substantially invariant clock signal loadingAT & T CORP·Filed 1994·Granted Apr 9, 1996·9 cites·14 claims
- 2340US6018480AMethod and system which permits logic signal routing over on-chip memoriesLSI LOGIC CORP·Filed 1998·Granted Jan 25, 2000·9 cites·10 claims
- 2438US5903505AMethod of testing memory refresh operations wherein subthreshold leakage current may be set to near worst-case conditionsLSI LOGIC CORP·Filed 1997·Granted May 11, 1999·9 cites·17 claims
- 2531US2006218455A1Integrated circuit margin stress test systemSILICON DESIGN SOLUTION INC·Filed 2005·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →