Inventor

LANE RICHARD H

81 patents

⚠️ This page may combine multiple inventors who share the name “LANE RICHARD H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LANE RICHARD H

MICRON TECHNOLOGY INC

Increased interior volume for integrated memory cell

Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry

Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry

Structures comprising transistor gates

Method of patterning noble metals for semiconductor devices by electropolishing

Methods of forming portions of transistor structures, methods of forming array peripheral circuitry, and structures comprising transistor gates

Method of forming a capacitor container electrode and method of patterning a metal layer by selectively silicizing the electrode or metal layer and removing the silicized portion

Method for fabricating conductive components in microelectronic devices and substrate structures thereof

Methods of forming capacitor constructions

Structures comprising transistor gates

Method of forming noble metal pattern

Structure for improving static refresh

Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry

Increased interior volume for integrated memory cell

Process for forming metalized contacts to periphery transistors

Isolation region forming methods

Isolation region forming methods

Methods and apparatuses for removing material from discrete areas on a semiconductor wafer

Semiconductor processing methods

Method for forming controlled geometry hardmasks including subresolution elements

Process for forming metallized contacts to periphery transistors

High-pressure anneal process for integrated circuits

High pressure anneal process for integrated circuits

Isolation region forming methods

Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry

High-pressure anneal process for integrated circuits

Isolation region forming methods

High-pressure anneal process for integrated circuits

Reverse metal process for creating a metal silicide transistor gate structure

Reverse metal process for creating a metal silicide transistor gate structure

Method of forming a mass over a semiconductor substrate

Method for forming conductive material in opening and structure regarding same

Isolation region forming methods

Method for forming conductive material in opening and structures regarding same

Reverse metal process for creating a metal silicide transistor gate structure

Semiconductor construction of a trench

Method of improving static refresh

High-pressure anneal process for integrated circuits

Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry

Method of improving static refresh

High-pressure anneal process for integrated circuits

Method of depositing an aluminum nitride comprising layer over a semiconductor substrate

Isolation region forming methods

Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry

Method for fabricating conductive components in microelectronic devices and substrate structures therefor

MOTOROLA INC

Self-aligned buried channel fabrication process

Expandable 4 × 8 array multiplier

SIGNETICS CORP

Protection device utilizing one or more subsurface diodes and associated method of manufacture

BIPOLAR INTEGRATED TECHNOLOGY

Gold interconnect with sidewall-spacers

GILGEN BRENT D

Methods of providing electrical isolation and semiconductor structures including same