Self-aligned buried channel fabrication process

Abstract

A technique is described for the preparation of buried channels of arbitrary conductivity type in a semiconductor device or integrated circuit containing oxide moats in an epitaxial surface layer. By following a specific sequence of process steps, two mask layers are obtained from a single mask alignment step which permits adjacent regions in the substrate to be doped to different conductivity and type, if desired, prior to the growth of the epitaxial layer. The resulting epitaxial layer has an irregular surface pattern reflecting the shape of the buried structures to faciliate ready alignment with the mask pattern necessary for the production of oxide moats. The resulting structure has a channel buried under the oxide moat region which is used to inhibit the formation of parasitic channels or create a desired channel for device purposes.

I claim: 
     
       1. A process for providing in a semiconductor wafer a buried region of a second dopant abutting a region of a first dopant, comprising the steps of: forming on said wafer a first mask pattern resistant to oxidation and a first dopant, and having at least a first opening;   applying said first dopant through said first opening;   forming without further mask alignment a second mask pattern coincident with said first opening having at least a second opening complementary to said first opening;   applying a second dopant through said second opening;   removing said first and second mask patterns; and   forming an epitaxial layer of a predetermined conductivity type and thickness on said semiconductor wafer.   
     
     
       2. The process of claim 1 wherein said first forming step further comprises forming a sandwich of a silicon dioxide layer on said wafer and a silicon nitride layer on said silicon dioxide layer. 
     
     
       3. The process of claim 2 further comprising the step of removing said silicon nitride layer prior to applying said second dopant. 
     
     
       4. The process of claim 1 wherein said second forming step further comprises forming said second mask pattern by oxidizing said wafer through said first opening in said first mask pattern layer. 
     
     
       5. The process of claim 4 wherein said second mask pattern formed by oxidation is at least twice as thick as said first mask pattern. 
     
     
       6. The process of claim 1 wherein said second dopant is of the same conductivity type as said semiconductor wafer and of opposite conductivity to said first dopant. 
     
     
       7. The process of claim 1 wherein said second dopant is of opposite conductivity type to said semiconductor wafer and of the same conductivity as said first dopant.