Inventor

HINTON GLENN J

US126 patents

⚠️ This page may combine multiple inventors who share the name “HINTON GLENN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HINTON GLENN J

INTEL CORP

Method and apparatus for processing memory-type information within a microprocessor

Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer

Method and apparatus for staggering execution of an instruction

Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state

Method and apparatus for blocking execution of and storing load operations during their execution

Speculative and committed resource files in an out-of-order processor

Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue

Method and apparatus for resolving return from subroutine instructions in a computer processor

Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor

Method and apparatus for implementing a set-associative branch target buffer

Circuit and method for scheduling instructions by predicting future availability of resources required for execution

Trace based instruction caching

Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit

Method and apparatus for dynamic allocation of multiple buffers in a processor

Method and apparatus for implementing a single clock cycle line replacement in a data cache unit

Way-predicting cache memory

Processor having execution core sections operating at different clock rates

Trace based instruction caching

Method and apparatus for providing a cache management technique

Flag renaming and flag masks within register alias table

Mechanism for efficiently overlapping multiple operand types in a microprocessor

Method and apparatus for implementing a branch target buffer in CISC processor

Method and apparatus for changing flow of control in a processor

Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor

Method and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessor

Method and apparatus for blocking execution of and storing load operations during their execution

Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor

Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers

Translation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of processing speculative instructions

Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system

Branch target buffer for dynamically predicting branch instruction outcomes using a predicted branch history

Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system

Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges

Method and apparatus for scheduling the dispatch of instructions from a reservation station

Idiom recognizer within a register alias table

Coordinating speculative and committed state register source data and immediate source data in a processor

Apparatus and method for maintaining processing consistency in a computer system having multiple processors

Staggering execution of a single packed data instruction using the same circuit

Method and apparatus for staggering execution of a single packed data instruction using the same circuit

Circuit and method for scheduling instructions by predicting future availability of resources required for execution

Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed

Apparatus and method for entry allocation for a resource buffer

System for executing different cycle instructions by selectively bypassing scoreboard register and canceling the execution of conditionally issued instruction if needed resources are busy

Two-level system main memory

Method and apparatus for performing error correction on data from an external memory

(unassigned)

Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations

INTEL CORPORAITON

Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers

DAHLEN ERIC J

Two-level system main memory

RAMANUJAN RAJ K

Apparatus and method for implementing a multi-level memory hierarchy having different operating modes

HINTON GLENN J

Microprocessor in which multiple instructions are executed in one clock cycle by providing separate machine bus access to a register file for different types of instructions