Microprocessor in which multiple instructions are executed in one clock cycle by providing separate machine bus access to a register file for different types of instructions

Abstract

A microprocessor having a memory coprocessor (10) connected to a MEM interface (16) and a register coprocessor (12) connected to a REG interface (14). The REG interface (14) and MEM interface (16) are connected to independent read and write ports of a register file (6). An Instruction Sequencer (7) also connected to an independent write port of the register file, to the REG interface and to the MEM interface. An Instruction Cache (9) supplies the instruction sequencer with at least two instruction words per clock (7). Single-cycle coprocessors (4) are connected to the REG interface (14) and a multiple-cycle coprocessors (2) are connected to the REG interface (14). An Address Generation Unit (3) is connected to the MEM interface (16) for executing load-effective-address instructions and address computations for loads and stores to thereby perform effective address calculations in parallel with instruction execution by the single-cycle coprocessor. The Instruction Sequencer (7) decodes incoming instruction words form the Cache, and issues up to three instructions on the REG interface (14), the MEM interface (16), and/or the branch logic within the Instruction Sequencer. The instruction sequencer includes means for detecting dependencies between the instructions to thereby prevent collisions between instructions. A local register cache (5) is provided connected to the MEM interface. The local register cache maintains a stack of multiple word local register sets, such that one each call the local registers are transferred from the register file (6) to the Local Register Cache (5) to thereby allocate the local registers in the register file for the called procedure and on a return the words are transferred back into the register file to the calling procedure.

What is claimed is: 
     
       1. A microprocessor comprising: a REG interface (14),   A MEM interface (16);   a macro bus (11);   an instruction cache (9) connected to this macro bus capable of supplying multiple instructions on said macro bus during a single clock cycle;   an instruction sequencer (7) connected to said macro bus, said REG interface, said MEM interface;   said instruction sequencer including an instruction decoder and a branch logic;   a multiported register file (6) connected to said instruction sequencer (7) capable of reading from multiple sources of instructions during a single clock cycle;   said instruction decoder within said instruction sequencer (7) being capable of decoding multiple instructions and issuing, multiple instructions during a single clock cycle on said REG interface, said MEM interface and said branch logic;   first coprocessors (2,4,12) connected in parallel to said REG interface for receiving first instructions having a first format from said register file and for executing said instructions in parallel during a single clock cycle; and,   second coprocessors (3,5,10) connected in parallel to said MEM interface for receiving second instructions having a second format from said register file and for executing said second instructions in parallel during a single clock cycle.   
     
     
       2. The combination in accordance with claim 1 further comprising: a local register cache (5) connected to said MEM interface for maintaining a stack of multiple-word local register sets, such that on each call the local registers are transferred from said register file (6) to said Local Register Cache (5) to thereby allocate said local registers in the register file for the called procedure and on a return said words are transferred back into the register file to the calling procedure.   
     
     
       3. The combination in accordance with claim 2 wherein said single-cycle coprocessor (4) is an integer execution unit (4); said execution unit being capable of executing integer arithmetic operations in a single cycle.   
     
     
       4. A microprocessor comprising: a REG interface (14);   a MEM interface (16);   a memory coprocessor (10) connected to said MEM interface (16);   a register coprocessor (12) connected to said REG interface (14);   an Instruction Sequencer (7);   a Register File (6) having a first independent read port, a second independent read port, a third independent read port, a fourth independent read port, a first independent write port and a second independent write port;   said REG interface (14) connected to said first and second independent read ports and said first independent wire port;   said MEM interface (16) connected to said third and fourth independent read ports and said second independent write port;   said Instruction Sequencer (7) connected to said REG interface and to said MEM interface;   an Instruction Cache (9) connected to said instruction sequencer and to said MEM interface for providing said Instruction Sequencer with instructions every cycle;   said Cache (9) being multiple words wide and capable of supplying at least two words per clock to said Instruction Sequencer (7);   a single-cycle coprocessor (4) connected to said REG interface (14);   a multiple-cycle coprocessor (2) connected to said REG interface (14);   said Multiply-Divide Unit including means for executing multiply and divide, arithmetic operations requiring multiple cycles; and,   an Address Generation Unit (3) connected to said MEM interface (16);   said Address Generation Unit including means for executing load-effective-address instructions and address computations for loads and stores to thereby perform effective address calculations in parallel with instruction execution by said integer execution unit;   said Instruction Sequencer (7) including means for decoding said incoming instruction words from said Cache, and issuing up to three instructions each on one of, said REG interface (14), said MEM interface (26), and said branch logic within said Instruction Sequencer, including means for detecting dependencies between the instructions to thereby prevent collisions between instructions.   
     
     
       5. The combination in accordance with claim 4 further comprising: a local register cache (5) connected to said MEM interface for maintaining a stack of multiple-word local register sets, such that on each call the local registers are transferred from said register file (6) to said Local Register Cache (5) to thereby allocate said local registers in the register file for the called procedure and on a return said words are transferred back into the register file to the calling procedure.   
     
     
       6. The combination in accordance with claim 4 wherein said single-cycle coprocessor (4) is an integer execution unit (4); said execution unit being capable of executing integer arithmetic operations in a single cycle.   
     
     
       7. The combination in accordance with claim 4 wherein said a multiple-cycle coprocessor is a multiply-divide unit (2); said Multiply-Divide Unit being capable of executing multiply and divide arithmetic operations requiring multiple cycles.   
     
     
       8. The combination in accordance with claim 4 wherein said a multiple-cycle coprocessor is a multiply-divide unit (2); said Multiply-Divide Unit being capable of executing multiply and divide arithmetic operations requiring multiple cycles.   
     
     
       9. In a five pipe-stage pipelined microprocessor which includes an instruction cache (9), an Instruction Sequencer (7) including branch logic, instruction pointer (IP), a REG interface (14), a MEM interface (16), register file (6) of registers including destinations registers, the method comprising the steps of: (A) accessing (104) said instruction cache (9) during the first pipe stage the Instruction Sequencer (7);   (B) transferring (106) from said I-Cache to said Instruction Sequencer (7) three or four instruction words depending on whether said instruction pointer (IP) points to an even or odd word address;   (C) decoding (108) said instructions in said Instruction Sequencer (7) during said second pipe stage;   (D) checking (110), during said second pipe stage, for dependencies between instructions;   (E) issuing (112), during said second pipe stage, up to three instructions on the three execution portions of the machine, said REG interface (14), said MEM interface (16), and said branch logic within said Instruction Sequencer (7), only the instructions that can be executed;   (F) reading (114) into said register file (6), during said second pipe stage, the sources for all the issued operations;   (G) sending (116) out of said register file (6), during said second pipe stage, said sources for all the issued operations to the respective units to use;   (H) calculating (118), during said second pipe stage, the new IP for branch operations;   (I) returning (122) to said register file, during said third pipe stage, the results of doing the EU (4) and/or the AGU (3) ALU/LDA operations; and,   (J) writing (124) said results into said destination registers of said register file.   
     
     
       10. The method in accordance with claim 9 comprising the further steps of: (K) issuing (128), during said third pipe stage, the address on the external address bus for loads and stores that go off-chip; and,   (L) placing (130) data on said external data bus during the fourth pipe stage; and,   (M) returning (132) from said bus controller (10) returns said data to said register file during the 5the pipe stage.