Inventor · disambiguated record
Robert T. Golla
Also filed as: GOLLA ROBERT · GOLLA ROBERT T · GOLLA ROBERT THADDEUS
77 granted patents·5 pending applications·1,048 citations·filing 1994–2022
99Inventor score
Top patents by PatentIndex Score
82 records- 0194US7478225B1Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processorSUN MICROSYSTEMS INC·Filed 2004·Granted Jan 13, 2009·100 cites·18 claims
- 0293US7185178B1Fetch speculation in a multithreaded processorSUN MICROSYSTEMS INC·Filed 2004·Granted Feb 27, 2007·90 cites·21 claims
- 0392US7509484B1Handling cache misses by selectively flushing the pipelineSUN MICROSYSTEMS INC·Filed 2004·Granted Mar 24, 2009·84 cites·21 claims
- 0489US8301865B2System and method to manage address translation requestsGROHOSKI GREGORY F·Filed 2009·Granted Oct 30, 2012·25 cites·20 claims
- 0586US9058180B2Unified high-frequency out-of-order pick queue with support for triggering early issue of speculative instructionsGOLLA ROBERT T·Filed 2009·Granted Jun 16, 2015·18 cites·20 claims
- 0686US8347309B2Dynamic mitigation of thread hogs on a threaded processorORACLE AMERICA INC·Filed 2009·Granted Jan 1, 2013·16 cites·18 claims
- 0785US8832464B2Processor and method for implementing instruction support for hash algorithmsOLSON CHRISTOPHER H·Filed 2009·Granted Sep 9, 2014·14 cites·20 claims
- 0885US7519796B1Efficient utilization of a store buffer using countersSUN MICROSYSTEMS INC·Filed 2004·Granted Apr 14, 2009·41 cites·15 claims
- 0984US7861063B1Delay slot handling in a processorORACLE AMERICA INC·Filed 2004·Granted Dec 28, 2010·36 cites·27 claims
- 1082US9262171B2Dependency matrix for the determination of load dependenciesGOLLA ROBERT T·Filed 2009·Granted Feb 16, 2016·13 cites·18 claims
- 1182US8560814B2Thread fairness on a multi-threaded processor with multi-cycle cryptographic operationsGOLLA ROBERT T·Filed 2010·Granted Oct 15, 2013·7 cites·20 claims
- 1282US8335912B2Logical map table for detecting dependency conditions between instructions having varying width operand valuesGOLLA ROBERT T·Filed 2009·Granted Dec 18, 2012·12 cites·18 claims
- 1381US8356185B2Apparatus and method for local operand bypassing for cryptographic instructionsORACLE AMERICA INC·Filed 2009·Granted Jan 15, 2013·10 cites·20 claims
- 1481US7401206B2Apparatus and method for fine-grained multithreading in a multipipelined processor coreSUN MICROSYSTEMS INC·Filed 2004·Granted Jul 15, 2008·29 cites·51 claims
- 1579US8769246B2Mechanism for selecting instructions for execution in a multithreaded processorGOLLA ROBERT T·Filed 2011·Granted Jul 1, 2014·4 cites·21 claims
- 1679US8335911B2Dynamic allocation of resources in a threaded, heterogeneous processorGOLLA ROBERT T·Filed 2009·Granted Dec 18, 2012·9 cites·17 claims
- 1778US8438208B2Processor and method for implementing instruction support for multiplication of large operandsOLSON CHRISTOPHER H·Filed 2009·Granted May 7, 2013·8 cites·20 claims
- 1878US7330988B2Method and apparatus for power throttling in a multi-thread processorSUN MICROSYSTEMS INC·Filed 2004·Granted Feb 12, 2008·23 cites·30 claims
- 1976US8099586B2Branch misprediction recovery mechanism for microprocessorsCHOU YUAN C·Filed 2008·Granted Jan 17, 2012·7 cites·17 claims
- 2076US7533248B1Multithreaded processor including a functional unit shared between multiple requestors and arbitration thereforSUN MICROSYSTEMS INC·Filed 2004·Granted May 12, 2009·21 cites·14 claims
- 2176US5634103AMethod and system for minimizing branch misprediction penalties within a processorIBM·Filed 1995·Granted May 27, 1997·79 cites·18 claims
- 2275US8429386B2Dynamic tag allocation in a multithreaded out-of-order processorJORDAN PAUL J·Filed 2009·Granted Apr 23, 2013·7 cites·15 claims
- 2375US8195923B2Methods and mechanisms to support multiple features for a number of opcodesSPRACKLEN LAWRENCE A·Filed 2009·Granted Jun 5, 2012·7 cites·20 claims
- 2472US5880983AFloating point split multiply/add system which has infinite precisionIBM·Filed 1996·Granted Mar 9, 1999·64 cites·42 claims
- 2571US8195919B1Handling multi-cycle integer operations for a multi-threaded processorOLSON CHRISTOPHER H·Filed 2007·Granted Jun 5, 2012·5 cites·19 claims
- 2670US8904156B2Perceptron-based branch prediction mechanism for predicting conditional branch instructions on a multithreaded processorSHAH MANISH K·Filed 2009·Granted Dec 2, 2014·5 cites·20 claims
- 2770US7890734B2Mechanism for selecting instructions for execution in a multithreaded processorOpen Computing Trust I & II·Filed 2004·Granted Feb 15, 2011·15 cites·40 claims
- 2870US7383403B1Concurrent bypass to instruction buffers in a fine grain multithreaded processorSUN MICROSYSTEMS INC·Filed 2004·Granted Jun 3, 2008·16 cites·16 claims
- 2968US7216216B1Register window management using first pipeline to change current window and second pipeline to read operand from old window and write operand to new windowSUN MICROSYSTEMS INC·Filed 2004·Granted May 8, 2007·13 cites·20 claims
- 3067US9665375B2Mitigation of thread hogs on a threaded processor and prevention of allocation of resources to one or more instructions following a load missCHOU YUAN C·Filed 2012·Granted May 30, 2017·2 cites·14 claims
- 3167US9122487B2System and method for balancing instruction loads between multiple execution units using assignment historyGOLLA ROBERT T·Filed 2009·Granted Sep 1, 2015·3 cites·17 claims
- 3267US8095778B1Method and system for sharing functional units of a multithreaded processorGOLLA ROBERT T·Filed 2004·Granted Jan 10, 2012·12 cites·21 claims
- 3366US7778105B2Memory with write port configured for double pump writeORACLE AMERICA INC·Filed 2008·Granted Aug 17, 2010·6 cites·7 claims
- 3466US7350053B1Software accessible fast VA to PA translationSUN MICROSYSTEMS INC·Filed 2005·Granted Mar 25, 2008·3 cites·15 claims
- 3565US8225034B1Hybrid instruction bufferGOLLA ROBERT T·Filed 2004·Granted Jul 17, 2012·11 cites·25 claims
- 3665US7343474B1Minimal address state in a fine grain multithreaded processorSUN MICROSYSTEMS INC·Filed 2004·Granted Mar 11, 2008·10 cites·30 claims
- 3763US10860326B2Multi-threaded instruction buffer designORACLE INT CORP·Filed 2019·Granted Dec 8, 2020·0 cites·20 claims
- 3863US7747771B1Register access protocol in a multihreaded multi-core processorORACLE AMERICA INC·Filed 2004·Granted Jun 29, 2010·9 cites·12 claims
- 3963US7523330B2Thread-based clock enabling in a multi-threaded processorSUN MICROSYSTEMS INC·Filed 2004·Granted Apr 21, 2009·8 cites·18 claims
- 4063US5898864AMethod and system for executing a context-altering instruction without performing a context-synchronization operation within high-performance processorsIBM·Filed 1997·Granted Apr 27, 1999·42 cites·12 claims
- 4161US11126577B2Distributed fairness protocol for interconnect networksORACLE INT CORP·Filed 2019·Granted Sep 21, 2021·0 cites·20 claims
- 4261US8504805B2Processor operating mode for mitigating dependency conditions between instructions having different operand sizesGOLLA ROBERT T·Filed 2009·Granted Aug 6, 2013·2 cites·16 claims
- 4360US11983538B2Load-store unit dual tags and replaysCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted May 14, 2024·0 cites·12 claims
- 4459US8195921B2Method and apparatus for decoding multithreaded instructions of a microprocessorGOLLA ROBERT·Filed 2008·Granted Jun 5, 2012·3 cites·14 claims
- 4558US9690625B2System and method for out-of-order resource allocation and deallocation in a threaded machineGOLLA ROBERT T·Filed 2009·Granted Jun 27, 2017·1 cites·19 claims
- 4658US8458446B2Accessing a multibank register file using a thread identifierOLSON CHRISTOPHER H·Filed 2009·Granted Jun 4, 2013·1 cites·20 claims
- 4758US7426630B1Arbitration of window swap operationsSUN MICROSYSTEMS INC·Filed 2004·Granted Sep 16, 2008·6 cites·19 claims
- 4858US5794024AMethod and system for dynamically recovering a register-address-table upon occurrence of an interrupt or branch mispredictionIBM·Filed 1996·Granted Aug 11, 1998·34 cites·15 claims
- 4957US11537505B2Forced debug mode entryCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Dec 27, 2022·0 cites·17 claims
- 5056US11531550B2Program thread selection between a plurality of execution pipelinesCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Dec 20, 2022·0 cites·20 claims
Showing the top 50 of 82 patent records by PatentIndex Score.
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