Inventor

JAMES DAVID V

US71 patents

⚠️ This page may combine multiple inventors who share the name “JAMES DAVID V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAMES DAVID V

APPLE COMPUTER

Multicasting system for selecting a group of memory devices for operation

Processor with sequences of processor instructions for locked memory updates

Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer system

System for transferring data specified in a transaction request as a plurality of move transactions responsive to receipt of a target availability signal

Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer system

Method and apparatus for using condition codes to nullify instructions based on results of previously-executed instructions on a computer processor

Elasticity buffer for data/clock synchronization

Self-correcting synchronization signal method and apparatus

Time multiplexing of cyclic redundancy functions in point-to-point ringlet-based computer systems

System and method for changing the states of directory-based caches and memories from read/write to read-only

System and method for efficiently routing data packets in a computer interconnect

DMA controller with mechanism for conditional action under control of status register, prespecified parameters, and condition field of channel command

System for finding and setting address portion of variable-length character string by XOR-ing portion in number of bytes within single instruction

Method and system for supporting multiprocessor TLB-purge instructions using directed write transactions

System for generating and sending a critical-world-first data response packet by creating response packet having data ordered in the order best matching the desired order

Apparatus and method for inter-node communication

System for and method of efficiently controlling memory accesses in a multiprocessor computer system

System and method for executing indivisible memory operations in multiple processor computer systems with multiple busses

System and method for preventing stale data in multiple processor computer systems

SONY CORP

Descriptor mechanism for assuring indivisible execution of AV/C operations

Method of and apparatus for implementing and sending an asynchronous control mechanism packet used to control bridge devices within a network of IEEE STD 1394 serial buses

Method and system for adjusting isochronous bandwidths on a bus

Method and system for circumscribing a topology to form ring structures

Method and system for the simplification of leaf-limited bridges

Method and system for quarantine during bus topology configuration

System and method for utilizing a memory device to support isochronous processes

Method and system for using a new bus identifier resulting from a bus topology change

Method and system for address spaces

System and method for delivering data packets in an electronic interconnect

CYPRESS SEMICONDUCTOR CORP

Cascadable content addressable memory (CAM) device and architecture

Data preclassifier method and apparatus for content addressable memory (CAM) device

Search engine device and method for generating output search responses from multiple input search responses

Method and apparatus for identifying content addressable memory device results for multiple requesting sources

Result compare circuit and method for content addressable memory (CAM) device

Method and apparatus for storing mask values in a content addressable memory (CAM) device

Device identification method for systems having multiple device branches

Content addressable memory (CAM) device decoder circuit

HEWLETT PACKARD CO

Direct input/output in a virtual memory system

Interrupt system using masking register in processor for selectively establishing device eligibility to interrupt a particular processor

Hybrid hardware/software method and apparatus for virtual memory address translation using primary and secondary translation buffers

Method and apparatus for performing variable length data read transactions

NETLOGIC MICROSYSTEMS INC

Apparatus and method for associating information values with portions of a content addressable memory (CAM) device

Content addressable memory (CAM) device having selectable access and method therefor

Packet based communication for content addressable memory (CAM) devices and systems

SONY ELECTRONICS INC

System and method for efficiently performing scheduling operations in an electronic device

Maintaining communications in a bus bridge interconnect

AV/C commands for accessing a hard disk device

ADVANCED MEMORY INTERNATIONAL

Memory system having synchronous-link DRAM (SLDRAM) devices and controller

Bifurcated data and command/address communication bus architecture for random access memories employing synchronous communication protocols

JAMES DAVID V

Method and apparatus for restricted search operation in content addressable memory (CAM) devices