Inventor
MUTHRASANALLUR SRIDHAR
US47 patents
⚠️ This page may combine multiple inventors who share the name “MUTHRASANALLUR SRIDHAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
30 patentsUS7210000B2Apr 24, 2007
Transmitting peer-to-peer transactions through a coherent interface
INTEL CORP51 citations96
US7949794B2May 24, 2011
PCI express enhancements and extensions
INTEL CORP41 citations95
US9116869B2Aug 25, 2015
Posting interrupts to virtual processors
INTEL CORP21 citations92
US7962771B2Jun 14, 2011
Method, system, and apparatus for rerouting interrupts in a multi-core processor
INTEL CORP28 citations92
US7930566B2Apr 19, 2011
PCI express enhancements and extensions
INTEL CORP13 citations92
US7899943B2Mar 1, 2011
PCI express enhancements and extensions
INTEL CORP16 citations92
US7627706B2Dec 1, 2009
Creation of logical APIC ID with cluster ID and intra-cluster ID
INTEL CORP22 citations91
US9575895B2Feb 21, 2017
Providing common caching agent for core and integrated input/output (IO) module
INTEL CORP5 citations84
US9535838B2Jan 3, 2017
Atomic operations in PCI express
INTEL CORP2 citations84
US9098415B2Aug 4, 2015
PCI express transaction descriptor
INTEL CORP4 citations84
US9032103B2May 12, 2015
Transaction re-ordering
INTEL CORP5 citations84
US9026682B2May 5, 2015
Prefectching in PCI express
INTEL CORP5 citations84
US7065597B2Jun 20, 2006
Method and apparatus for in-band signaling of runtime general purpose events
INTEL CORP17 citations84
US7769938B2Aug 3, 2010
Processor selection for an interrupt identifying a processor cluster
INTEL CORP18 citations82
US7734847B2Jun 8, 2010
Apparatus to maximize buffer utilization in an I/O controller
INTEL CORP9 citations80
US7441055B2Oct 21, 2008
Apparatus and method to maximize buffer utilization in an I/O controller
INTEL CORP11 citations80
US7461218B2Dec 2, 2008
Size-based interleaving in a packet-based link
INTEL CORP12 citations78
US12360934B2Jul 15, 2025
Parameter exchange for a die-to-die interconnect
INTEL CORP2 citations74
US7676603B2Mar 9, 2010
Write combining protocol between processors and chipsets
INTEL CORP6 citations74
US11520498B2Dec 6, 2022
Memory management to improve power performance
INTEL CORP4 citations67
US9892069B2Feb 13, 2018
Posting interrupts to virtual processors
INTEL CORP1 citations63
US9442855B2Sep 13, 2016
Transaction layer packet formatting
INTEL CORP1 citations63
US8843683B2Sep 23, 2014
Posting interrupts to virtual processors
INTEL CORP3 citations63
US7120722B2Oct 10, 2006
Using information provided through tag space
INTEL CORP6 citations63
US12505065B2Dec 23, 2025
On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHY
INTEL CORP0 citations62
US12499019B2Dec 16, 2025
Retimers to extend a die-to-die interconnect
INTEL CORP0 citations62
US12578384B2Mar 17, 2026
Unified test and debug chiplet architecture
INTEL CORP0 citations61
US9442868B2Sep 13, 2016
Delivering interrupts directly to a virtual processor
INTEL CORP0 citations52
US9552308B2Jan 24, 2017
Early wake-warn for clock gating control
INTEL CORP0 citations51
US11514551B2Nov 29, 2022
Configuration profiles for graphics processing unit
INTEL CORP0 citations48
AJANOVIC JASMIN
9 patentsUS8230120B2Jul 24, 2012
PCI express enhancements and extensions
AJANOVIC JASMIN21 citations96
US8555101B2Oct 8, 2013
PCI express enhancements and extensions
AJANOVIC JASMIN7 citations92
US8549183B2Oct 1, 2013
PCI express enhancements and extensions
AJANOVIC JASMIN8 citations92
US8473642B2Jun 25, 2013
PCI express enhancements and extensions including device window caching
AJANOVIC JASMIN6 citations92
US8447888B2May 21, 2013
PCI express enhancements and extensions
AJANOVIC JASMIN8 citations92
US8230119B2Jul 24, 2012
PCI express enhancements and extensions
AJANOVIC JASMIN14 citations92
US8099523B2Jan 17, 2012
PCI express enhancements and extensions including transactions having prefetch parameters
AJANOVIC JASMIN16 citations92
US8073981B2Dec 6, 2011
PCI express enhancements and extensions
AJANOVIC JASMIN14 citations92
US8793404B2Jul 29, 2014
Atomic operations
AJANOVIC JASMIN5 citations84