Apparatus and method to maximize buffer utilization in an I/O controller

Abstract

An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates to a chipset connected to the I/O controller the amount of available memory credits. The chipset may then send an amount of data to the I/O controller equivalent to or less than the communicated available amount of memory credits to reduce the occurrence of a “retry” event. The amount of available memory credits is determined by comparing the available memory in each buffer within the I/O controller and designating that the “available” amount of memory for the I/O controller is an amount equivalent to the amount of memory contained in the buffer with the least amount of available memory. This “available” amount of I/O controller memory may then be converted into memory credits and communicated to the chipset.

The invention claimed is: 
     
       1. A method comprising:
 determining an amount of available memory credits in an input/output (I/O) controller; 
 communicating to a chipset within a device coupled to the I/O controller within the device the amount of available memory credits, the amount of available memory credits being a specific number of available memory credits; and 
 sending an amount of data from the chipset to the I/O controller, the amount of data sent being one of equivalent to or less than the communicated available memory credit amount. 
 
     
     
       2. The method of  claim 1 , wherein determining the available amount of memory credits comprises:
 determining a least amount of available memory in one of a plurality of buffers to create an amount of available memory in an I/O controller. 
 
     
     
       3. The method of  claim 2 , further comprising:
 converting the amount of available memory in the I/O controller to the amount of available memory credits. 
 
     
     
       4. The method of  claim 3 , wherein converting the amount of available memory to an amount of available memory credits comprises:
 dividing the available amount of memory in the I/O controller by an amount of memory equivalent to one credit. 
 
     
     
       5. The method of  claim 2 , further comprising:
 temporarily storing the data sent from the chipset in the I/O controller. 
 
     
     
       6. The method of  claim 5 , wherein temporarily storing the data comprises:
 temporarily storing the data in at least one buffer contained within the I/O controller. 
 
     
     
       7. The method of  claim 6 , wherein temporarily storing the data in at least one buffer comprises:
 storing the data in a plurality of buffers. 
 
     
     
       8. The method of  claim 6 , further comprising:
 emptying the buffer of at least some of the data temporarily stored in the I/O controller to create a new amount of available memory credits in the I/O controller. 
 
     
     
       9. The method of  claim 8 , wherein emptying at least some of the data comprises:
 sending the data to at least one I/O bus coupled to the I/O controller. 
 
     
     
       10. The method of  claim 9 , wherein sending the data to at least one I/O bus comprises:
 sending the data to a plurality of I/O buses coupled to the I/O controller. 
 
     
     
       11. The method of  claim 8 , further comprising:
 keeping track of the number of available memory credits in the I/O controller. 
 
     
     
       12. The method of  claim 11 , wherein keeping track of the number of memory credits comprises:
 simultaneously keeping track of amounts of memory credits the I/O controller empties onto the I/O bus, amounts of memory credits sent to an I/O controller and amounts of memory credits made available by distribution of data sent from the chipset to a plurality of buffers contained within the I/O controller. 
 
     
     
       13. The method of  claim 1 , wherein the chipset directs data flow between a memory device and the I/O controller, and
 wherein the chipset communicates with the I/O controller over a bus within the device. 
 
     
     
       14. The method of  claim 13 , wherein the I/O controller directs data flow between the chipset and a set of I/O buses. 
     
     
       15. A non-transitory machine readable medium having instructions stored therein which when executed cause a machine to perform a set of operations comprising:
 determining an amount of available memory credits in an input/output (I/O) controller; 
 communicating to a chipset within a device coupled to the I/O controller within the device the amount of available memory credits, the amount of available memory credits being a specific number of available memory credits; and 
 sending an amount of data from the chipset to the I/O controller, the amount of data sent being one of equivalent to or less than the communicated available memory credit amount. 
 
     
     
       16. The non-transitory machine readable medium of  claim 15 , wherein determining the available amount of memory credits comprises:
 determining a least amount of available memory in one of a plurality of buffers to create an amount of available memory in a I/O controller. 
 
     
     
       17. The non-transitory machine read medium of  claim 16 , having further instructions stored therein which when executed cause a machine to perform a set of operations further comprising:
 temporarily storing the data in at least one buffer contained within the I/O controller;
 emptying the buffer of at least some of the data temporarily stored in the I/O controller onto an I/O bus coupled to the I/O controller to create a new amount of available memory credits in the I/O controller; and 
 simultaneously tracking amounts of memory credits the I/O controller empties onto the I/O bus, amounts of memory credits sent to the I/O controller from the chipset and amounts of memory credits made available by distribution of the data sent from the chipset to a plurality of buffers contained within the I/O controller. 
 
 
     
     
       18. The non-transitory machine readable medium of  claim 15 , wherein the chipset directs data flow between a memory device and the I/O controller, and
 wherein the chipset communicates with the I/O controller over a bus within the device. 
 
     
     
       19. The non-transitory machine readable medium of  claim 18 , wherein the I/O controller directs data flow between the chipset and a set of I/O buses.