Inventor · disambiguated record
Andres R. Takach
Also filed as: TAKACH ANDRES · TAKACH ANDRES R · TAKACH ANDRES RAFAEL
9 granted patents·1 pending application·150 citations·filing 2001–2017
89Inventor score
Technology areasG06F
Files withGUTBERLET PETER PIUS2MENTOR GRAPHICS CORP2WATERS SIMON JOSHUA2CALYPTO DESIGN SYSTEMS INC1CONDON ROBERT J1
Top patents by PatentIndex Score
10 records- 0191US6701501B2Structured algorithmic programming language approach to system designFiled 2001·Granted Mar 2, 2004·73 cites·37 claims
- 0289US9817929B1Formal verification using microtransactionsCALYPTO DESIGN SYSTEMS INC·Filed 2015·Granted Nov 14, 2017·10 cites·32 claims
- 0387US10515168B1Formal verification using microtransactionsMENTOR GRAPHICS CORP·Filed 2017·Granted Dec 24, 2019·6 cites·20 claims
- 0485US8205175B2Structured algorithmic programming language approach to system designWATERS SIMON JOSHUA·Filed 2007·Granted Jun 19, 2012·14 cites·17 claims
- 0576US7840931B2Loop manipulation if a behavioral synthesis toolMENTOR GRAPHICS CORP·Filed 2008·Granted Nov 23, 2010·8 cites·14 claims
- 0675US7308672B2Structured algorithmic programming language approach to system designWATERS SIMON JOSHUA·Filed 2004·Granted Dec 11, 2007·19 cites·15 claims
- 0771US7353491B2Optimization of memory accesses in a circuit designGUTBERLET PETER PIUS·Filed 2005·Granted Apr 1, 2008·6 cites·14 claims
- 0866US7412684B2Loop manipulation in a behavioral synthesis toolGUTBERLET PETER PIUS·Filed 2004·Granted Aug 12, 2008·12 cites·27 claims
- 0955US8219949B2Nonsequential hardware design synthesis verificationCONDON ROBERT J·Filed 2010·Granted Jul 10, 2012·2 cites·17 claims
- 1038US2011035204A1Layered Modeling for High-Level Synthesis of Electronic DesignsSMIRNOV MAXIM·Filed 2010·Application pending·0 cites
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