Inventor

KUSKO MARY P

US72 patents

⚠️ This page may combine multiple inventors who share the name “KUSKO MARY P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KUSKO MARY P

IBM

Look ahead scan chain diagnostic method

Method and apparatus for programmable LBIST channel weighting

Technique to decrease the exposure time of infrared imaging of semiconductor chips for failure analysis

Partitioned pseudo-random logic test for improved manufacturability of semiconductor chips

Dynamic fault model generation for diagnostics simulation and pattern generation

Shared channel masks in on-product test compression system

Optimizing generation of test configurations for built-in self-testing

Adjusting latency in a scan cell

Iterative N-detect based logic diagnostic technique

Dynamic fault model generation for diagnostics simulation and pattern generation

Chip testing with exclusive OR

Logic built in self test circuitry for use in an integrated circuit with scan chains

Logic built in self test circuitry for use in an integrated circuit with scan chains

Logic built in self test circuitry for use in an integrated circuit with scan chains

Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry

Design-based weighting for logic built-in self-test

Method and apparatus for facilitating random pattern testing of logic structures

System testing using partitioned and controlled noise

Portion isolation architecture for chip isolation test

Managing chip testing data

Method for enhancing the diagnostic accuracy of a VLSI chip

Structurally assisted functional test and diagnostics for integrated circuits

Implementing MISR compression methods for test time reduction

Operating pulsed latches on a variable power supply

Reducing power requirements and switching during logic built-in-self-test and scan test

Apparatus and method for improved test controllability and observability of random resistant logic

Built-in device testing of integrated circuits

Scan chain latency reduction

Functional diagnostics based on dynamic selection of alternate clocking

Functional diagnostics based on dynamic selection of alternate clocking

Iterative N-detect based logic diagnostic technique

Dynamic fault model generation for diagnostics simulation and pattern generation

Collecting diagnostic data from chips

Shared channel masks in on-product test compression system

Collecting diagnostic data from chips

Chip testing with exclusive OR

Hierarchal test block test pattern reduction in on-product test compression system

Hierarchal test block test pattern reduction in on-product test compression system

Logic built in self test circuitry for use in an integrated circuit with scan chains

Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry

Bypassing an encoded latch on a chip during a test-pattern scan

Bypassing an encoded latch on a chip during a test-pattern scan

User privacy for autonomous vehicles

Dynamic weight selection process for logic built-in self test

Logic built-in self test dynamic weight selection method

Operating pulsed latches on a variable power supply

Minimization of over-masking in an on product multiple input signature register (OPMISR)

Implementing over-masking removal in an on product multiple input signature register (OPMISR) test due to common channel mask scan registers (CMSR) loading

DESINENI RAO H

Insertion of faults in logic model used in simulation

KUSKO MARY P

Automated file relocation