Inventor

WU CHING-WEI

TW83 patents

⚠️ This page may combine multiple inventors who share the name “WU CHING-WEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WU CHING-WEI

TAIWAN SEMICONDUCTOR MFG CO LTD

System and method for memory scan design-for-test

Static random access memory and method of controlling the same

Method of certifying safety levels of semiconductor memories in integrated circuits

Shared decoder circuit and method

Memory cell array including a write-assist circuit and embedded coupling capacitor and method of forming same

Scan synchronous-write-through testing architectures for a memory device

Integrated circuit with asymmetric arrangements of memory arrays

Scan synchronous-write-through testing architectures for a memory device

Two-stage read/write 3D architecture for memory devices

Time division multiplexed multiport memory

Latch circuit, memory device and method

Latch circuit, memory device and method

Circuit and method of writing to a bit cell

Memory circuits with dynamically adjustable pulse widths and methods for operating the same

Sub-word line driver placement for memory device

Sub-word line driver placement for memory device

Sub-word line driver placement for memory device

Sub-word line driver placement for memory device

Integrated circuit with asymmetric arrangements of memory arrays

Integrated circuit with asymmetric arrangements of memory arrays

Circuit and method of operating the same

Memory circuit and method of operating the same

Integrated circuit with asymmetric arrangements of memory arrays

Memory circuit and method of operating the same

Integrated circuit with asymmetric arrangements of memory arrays

Method of certifying safety levels of semiconductor memories in integrated circuits

Circuit and method of operating the same

Memory circuit and method of operating the same

Memory macro and method of operating the same

Method of detecting address decoding error

Method of detecting address decoding error and address decoder error detection system

Scan synchronous-write-through testing architectures for a memory device

Shared decoder circuit and method

Latch circuit and memory device

Shared decoder circuit and method

Shared decoder circuit and method

Scan synchronous-write-through testing architectures for a memory device

Read-only memory method, layout, and device

Memory device

TAIWAN SEMICONDUCTOR MFG

Word-line driver design for pseudo two-port memories

Multiple-time programmable electrical fuse utilizing MOS oxide breakdown

Three-dimensional two port register file

SRAM cell array structure

Simultaneous two/dual port access on 6T SRAM

SRAM device with enhanced read/write operations

N-bit rom cell

WU CHING-WEI

Asymmetric sense amplifier design

Read only memory and operating method thereof

LIN TZU-KUEI

Memory device having a clock skew generator

LEE CHENG HUNG

Memory circuits, systems, and methods for routing the memory circuits