Latch circuit, memory device and method

Abstract

A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. The latch clock generator includes a first inverter configured to generate an inverted signal of the first enable signal, and a NAND gate coupled to the first inverter to receive the inverted signal of the first enable signal. The NAND gate is configured to generate the latched clock signal based on the clock signal and the inverted signal of the first enable signal.

What is claimed is: 
     
       1. A latch circuit, comprising:
 a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal; and 
 an input latch coupled to the latch clock generator to receive the latched clock signal, the input latch configured to generate a latched output signal based on the latched clock signal and an input signal, 
 wherein, in response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal, 
 wherein the latch clock generator comprises: a NAND gate and a transistor, 
 wherein the NAND gate comprises:
 a first input configured to receive a signal corresponding to the first enable signal, 
 a second input coupled to an internal node to receive an internal clock signal corresponding to the clock signal, and 
 an output at which the NAND gate is configured to output the latched clock signal, and 
 
 wherein the transistor comprises:
 a first terminal coupled to a node of a power supply voltage, 
 a second terminal coupled to the internal node, and 
 a gate terminal configured to receive a second enable signal. 
 
 
     
     
       2. The latch circuit of  claim 1 , wherein
 in response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings while the latched clock signal is having the corresponding disabling logic level. 
 
     
     
       3. The latch circuit of  claim 2 , wherein
 in response to the first enable signal having an enabling logic level different from the disabling logic level,
 the latch clock generator is configured to switch the logic level of the latched clock signal in accordance with the clock signal, and 
 in response to the switched logic level of the latched clock signal, the input latch is configured to switch the logic level of the latched output signal in accordance with the input signal. 
 
 
     
     
       4. The latch circuit of  claim 1 , further comprising:
 an enable latch configured to generate the first enable signal based on the clock signal and a further enable signal, 
 wherein the latch clock generator is coupled to the enable latch to receive the first enable signal. 
 
     
     
       5. The latch circuit of  claim 1 , further comprising:
 an OR gate configured to generate the first enable signal based on further enable signals, 
 wherein the latch clock generator is coupled to the OR gate to receive the first enable signal. 
 
     
     
       6. The latch circuit of  claim 1 , wherein
 the latch clock generator further comprises:
 first and second transistors serially coupled between the internal node and the node of the power supply voltage, and 
 third and fourth transistors coupled in parallel between the internal node and a further node, 
 
 gate terminals of the first and third transistors are configured to receive an inverted signal of the clock signal, and 
 gate terminals of the second and fourth transistors are configured to receive the clock signal. 
 
     
     
       7. A memory device, comprising:
 a memory cell; and 
 a control circuit coupled to control an operation of the memory cell, the control circuit comprising:
 a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal; and 
 an input latch coupled to the latch clock generator to receive the latched clock signal, the input latch configured to generate a latched output signal based on the latched clock signal and an input signal, 
 
 wherein the enable signal corresponds to
 a chip enable signal to enable or disable the memory device. 
 
 
     
     
       8. The memory device of  claim 7 , wherein
 the input signal comprises one of
 a data signal containing data to be written to the memory cell, 
 a bit-write-mask signal to control selective writing to the memory cell, or 
 an address signal containing an address of the memory cell. 
 
 
     
     
       9. The memory device of  claim 7 , wherein
 the input signal comprises a bit-write-mask signal to control selective writing to the memory cell. 
 
     
     
       10. The memory device of  claim 7 , wherein
 the input signal comprises one of
 a data signal containing data to be written to the memory cell, or 
 a bit-write-mask signal to control selective writing to the memory cell. 
 
 
     
     
       11. The memory device of  claim 7 , wherein
 the input signal comprises one of
 an address signal containing an address of the memory cell, or 
 a bit-write-mask signal to control selective writing to the memory cell. 
 
 
     
     
       12. The memory device of  claim 7 , wherein
 the latch clock generator comprises a NAND gate configured to
 receive the clock signal and an inverted signal of the enable signal, and 
 generate a signal corresponding to the latched clock signal, based on the clock signal and the inverted signal of the enable signal. 
 
 
     
     
       13. A method of operating a memory device having a memory cell, the method comprising:
 generating an internal clock signal based on a clock signal and a first enable signal; 
 generating a latched clock signal based on the internal clock signal and a second enable signal; and 
 generating a latched output signal for controlling an operation of the memory cell based on the latched clock signal and an input signal, 
 wherein 
 in said generating the latched clock signal,
 in response to the second enable signal having a disabling logic level, a logic level of the latched clock signal is set to a corresponding disabling logic level regardless of the clock signal and the first enable signal, and 
 
 in said generating the latched output signal,
 in response to the corresponding disabling logic level of the latched clock signal, a logic level of the latched output signal is held unchanged regardless of the input signal having one or more logic level switchings while the second enable signal is having the disabling logic level. 
 
 
     
     
       14. The method of  claim 13 , wherein
 in said generating the internal clock signal,
 in response to the first enable signal having a disabling logic level, a logic level of the internal clock signal is held unchanged regardless of the clock signal, and 
 in response to the first enable signal having an enabling logic level, the logic level of the internal clock signal is switched in accordance with the clock signal, 
 
 in said generating the latched clock signal,
 in response to the logic level of the internal clock signal being switched in accordance with the clock signal and the second enable signal having an enabling logic level different from the disabling logic level, the logic level of the latched clock signal is switched in accordance with the clock signal, and 
 
 in said generating the latched output signal,
 in response to the switched logic level of the latched clock signal, the logic level of the latched output signal is switched in accordance with the input signal. 
 
 
     
     
       15. The method of  claim 13 , wherein
 the second enable signal corresponds to at least one of
 a chip enable signal to enable or disable the memory device, or 
 a write enable signal to enable or disable writing to the memory cell. 
 
 
     
     
       16. The method of  claim 15 , wherein
 the input signal comprises one of
 a data signal containing data to be written to the memory cell, 
 a bit-write-mask signal to control selective writing to the memory cell, or 
 an address signal containing an address of the memory cell. 
 
 
     
     
       17. The method of  claim 13 , wherein at least one of
 the second enable signal corresponds to a chip enable signal to enable or disable the memory device, or 
 the input signal comprises a bit-write-mask signal to control selective writing to the memory cell. 
 
     
     
       18. The latch circuit of  claim 1 , wherein
 the latch clock generator further comprises a first inverter comprising:
 an input configured to receive the first enable signal, and 
 an output coupled to the first input of the NAND gate. 
 
 
     
     
       19. The latch circuit of  claim 18 , wherein
 the latch clock generator further comprises second and third inverters serially connected to the output of the NAND gate. 
 
     
     
       20. The memory device of  claim 12 , wherein
 the NAND gate comprises:
 a first input configured to receive the inverted signal of the enable signal, and 
 a second input coupled to an internal node to receive an internal clock signal corresponding to the clock signal, and 
 
 the transistor comprises:
 a first terminal coupled to a node of a power supply voltage, 
 a second terminal coupled to the internal node, and 
 a gate terminal configured to receive a further enable signal.