Inventor

POWELL STEPHEN J

US44 patents

⚠️ This page may combine multiple inventors who share the name “POWELL STEPHEN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

POWELL STEPHEN J

IBM

Dynamically adjusting read data return sizes based on memory interface bus utilization

Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system

Synchronization and order detection in a memory system

Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system

Address/command chip controlled data chip address sequencing for a distributed memory buffer system

Partial data replay in a distributed memory buffer system

Synchronization and order detection in a memory system

Modification of prefetch depth based on high latency event

Least-recently-used (LRU) to first-dirty-member distance-maintaining cache cleaning scheduler

Method and apparatus for mitigating effects of memory scrub operations on idle time power savings modes

Speculative bank activate dynamic random access memory (DRAM) scheduler

Information handling system with immediate scheduling of load operations

Speculative bank activate dynamic random access memory (DRAM) scheduler

Least-recently-used (LRU) to first-dirty-member distance-maintaining cache cleaning scheduler

Memory uncorrectable error handling technique for reducing the impact of noise

Memory uncorrectable error handling technique for reducing the impact of noise

Host synchronized autonomous data chip address sequencer for a distributed buffer memory system

Address/command chip controlled data chip address sequencing for a distributed memory buffer system

Refresh-hiding memory system staggered refresh

Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system

Modification of prefetch depth based on high latency event

DRAM bank activation management

DRAM bank activation management

Reduced system memory latency via a variable latency interface

Interface scheduler for a distributed memory system

Host synchronized autonomous data chip address sequencer for a distributed buffer memory system

Partial data replay in a distributed memory buffer system

Synchronization and order detection in a memory system

Early data tag to allow data CRC bypass via a speculative memory data return protocol

Early data tag to allow data CRC bypass via a speculative memory data return protocol

Memory request scheduling to improve bank group utilization

Method for scheduling memory refresh operations including power states

Decoding and executing memory command with partial frame data

Method and apparatus for mitigating effects of memory scrub operations on idle time power savings mode

Host controlled data chip address sequencing for a distributed memory buffer system

DALY DAVID M

Weighted history allocation predictor algorithm in a hybrid cache

Weighted history allocation predictor algorithm in a hybrid cache

Dynamic inclusive policy in a hybrid cache hierarchy using hit rate

Dynamic inclusive policy in a hybrid cache hierarchy using bandwidth

BRITTAIN MARK A

Memory queue handling techniques for reducing impact of high-latency memory operations

Memory reorder queue biasing preceding high latency operations

Apparatus for scheduling memory refresh operations including power states

CARGNONI ROBERT A

Load request scheduling in a cache hierarchy

GLOBALFOUNDRIES INC

Dynamic write priority based on virtual write queue high water mark for set associative cache using cache cleaner when modified sets exceed threshold