Interface scheduler for a distributed memory system

Abstract

An Address and Command chip of a distributed memory system includes a memory controller, a first communication link, and one or more interface schedulers, where the one or more interface schedulers include a first interface scheduler residing communicatively between the memory controller and the first communication link. The first interface scheduler is configured to receive a first communication directed from the memory controller to the first communication link; capture the first communication before the first command reaches the first communication link; postpone the first communication for a first set of one or more memory cycles; and reissue the first communication to the first communication link in association with a first cycle offset code indicating how many memory cycles the first command was postponed.

What is claimed is: 
     
       1. A computer-implemented method comprising:
 receiving, by a first interface scheduler in communication with a memory controller, a first communication directed from the memory controller to a target component; 
 capturing the first communication before the first communication reaches the target component; 
 postponing the first communication for a first set of one or more memory cycles; and 
 reissuing the first communication to the target component in association with a first cycle offset code indicating how many memory cycles the first communication was postponed, wherein the first interface scheduler resides communicatively between the memory controller and a data chip in a distributed memory system, and wherein the capturing the first communication before the first communication reaches the target component comprises capturing a command before the command reaches the data chip. 
 
     
     
       2. The computer-implemented method of  claim 1 , wherein the cycle offset code indicates an offset useable to calculate a fixed delay until data arrives at the target component. 
     
     
       3. The computer-implemented method of  claim 1 , wherein the first interface scheduler resides communicatively between the memory controller and a host processor, and wherein the capturing the first communication before the first communication reaches the target component comprises capturing a response before the response reaches the host processor. 
     
     
       4. The computer-implemented method of  claim 1 , wherein the target component is a host processor, and the computer-implemented method further comprising:
 receiving, by a second interface scheduler in communication with the memory controller, a second communication directed from the memory controller to a data chip of a distributed memory system; 
 capturing the second communication before the second communication reaches the data chip; 
 postponing the second communication for a second set of one or more memory cycles; and 
 reissuing the second communication to the data chip in association with a second cycle offset code indicating how many memory cycles the second communication was postponed. 
 
     
     
       5. The computer-implemented method of  claim 1 , wherein:
 the capturing the first communication before the first communication reaches the target component comprises capturing a read response before the read response reaches a host processor; 
 the reissuing the first communication to the target component in association with the first cycle offset code comprises reissuing the read response to the host processor in association with the first cycle offset code; and 
 the first cycle offset code is useable by the host processor to determine when data on a high-speed serial link becomes valid. 
 
     
     
       6. The computer-implemented method of  claim 1 , wherein:
 the capturing the first communication before the first communication reaches the target component comprises capturing the first communication before the first communication reaches a data chip in a distributed memory system; 
 the first communication is at least one of a fetch command, a store-from-buffer command, and a write-to-buffer command; 
 the reissuing the first communication to the target component in association with the first cycle offset code comprises reissuing the first communication to the data chip in association with the first cycle offset code; and 
 the first cycle offset code is useable by the data chip to determine when data on a data buffer control/communication link becomes valid. 
 
     
     
       7. The computer-implemented method of  claim 1 , wherein the memory controller is a dual-port memory controller. 
     
     
       8. An Address and Command chip (AC) in a distributed memory system, the AC comprising:
 a memory controller; 
 a first communication link; and 
 one or more interface schedulers, comprising a first interface scheduler residing communicatively between the memory controller and the first communication link; 
 wherein the first interface scheduler is configured to:
 receive a first communication directed from the memory controller to the first communication link; 
 capture the first communication before the first command reaches the first communication link; 
 postpone the first communication for a first set of one or more memory cycles; and 
 reissue the first communication to the first communication link in association with a first cycle offset code indicating how many memory cycles the first command was postponed, wherein the first communication link is a data buffer control/communication link to a data chip in a distributed memory system, and wherein the first interface scheduler is configured to capture the first communication before the first communication reaches the data chip. 
 
 
     
     
       9. The AC of  claim 8 , wherein the cycle offset code indicates an offset useable to calculate a fixed delay until data arrives at the target component. 
     
     
       10. The AC of  claim 8 , wherein the first communication link is a high-speed serial link to a host processor, and wherein the first interface scheduler is configured to capture the first communication before the first communication reaches the host processor. 
     
     
       11. The AC of  claim 8 , wherein first communication link is a high-speed serial link to a host processor, and the AC further comprising:
 a data buffer control/communication (BCOM) link to a data chip of a distributed memory system; and 
 a second interface scheduler residing communicatively between the memory controller and the BCOM link; 
 wherein the second interface scheduler is configured to:
 receive a command directed from the memory controller to the BCOM link; 
 capture the command before the command reaches the BCOM link; 
 postpone the command for a second set of one or more memory cycles; and 
 reissue the command to the BCOM link in association with a second cycle offset code indicating how many memory cycles the command was postponed. 
 
 
     
     
       12. The AC of  claim 8 , wherein:
 the first communication is a read response; 
 the first communication link is a high-speed serial link to a host processor; and 
 the first cycle offset code is useable by the host processor to determine when data on the high-speed serial link becomes valid. 
 
     
     
       13. The AC of  claim 8 , wherein:
 the first command is at least one of a fetch command, a store-from-buffer command, and a write-to-buffer command; 
 the first communication link is a data buffer control/communication (BCOM) link to a data chip in a distributed memory system; and 
 the first cycle offset code is useable by the data chip to determine when data on the BCOM link becomes valid. 
 
     
     
       14. A distributed memory system comprising:
 a dynamic random-access memory (DRAM) 
 at least one data chip in communication with the DRAM; and 
 an Address and Command chip (AC) in communication with the DRAM, the at least one data chip, and a host processor; 
 wherein the AC comprises:
 a memory controller; 
 a first communication link; and 
 one or more interface schedulers, comprising a first interface scheduler residing communicatively between the memory controller and the first communication link; 
 wherein the first interface scheduler is configured to:
 receive a first communication directed from the memory controller to the first communication link; 
 capture the first communication before the first command reaches the first communication link; 
 postpone the first communication for a first set of one or more memory cycles; and 
 reissue the first communication to the first communication link in association with a first cycle offset code indicating how many memory cycles the first command was postponed wherein the first communication link is a data buffer control/communication link to the data chip, and wherein the first interface scheduler is configured to capture the first communication before the first communication reaches the data chip. 
 
 
 
     
     
       15. The distributed memory system of  claim 14 , wherein the first communication link is a high-speed serial link to the host processor, and wherein the first interface scheduler is configured to capture the first communication before the first communication reaches the host processor. 
     
     
       16. The distributed memory system of  claim 14 , wherein first communication link is a high-speed serial link to a host processor, and wherein the AC further comprises:
 a data buffer control/communication (BCOM) link to the data chip; and 
 a second interface scheduler residing communicatively between the memory controller and the BCOM link; 
 wherein the second interface scheduler is configured to:
 receive a command directed from the memory controller to the BCOM link; 
 capture the command before the command reaches the BCOM link; 
 postpone the command for a second set of one or more memory cycles; and 
 reissue the command to the BCOM link in association with a second cycle offset code indicating how many memory cycles the command was postponed. 
 
 
     
     
       17. The distributed memory system of  claim 14 , wherein:
 the first communication is a read response command; 
 the first communication link is a high-speed serial link to the host processor; and 
 the first cycle offset code is useable by the host processor to determine when data on the high-speed serial link becomes valid.