Inventor · disambiguated record
Stephen J. Powell
Also filed as: POWELL STEPHEN · POWELL STEPHEN J
47 granted patents·2 pending applications·156 citations·filing 2009–2021
97Inventor score
Top patents by PatentIndex Score
49 records- 0196US9684461B1Dynamically adjusting read data return sizes based on memory interface bus utilizationIBM·Filed 2016·Granted Jun 20, 2017·20 cites·17 claims
- 0291US11379123B2Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory systemIBM·Filed 2021·Granted Jul 5, 2022·2 cites·17 claims
- 0391US9430418B2Synchronization and order detection in a memory systemIBM·Filed 2013·Granted Aug 30, 2016·11 cites·17 claims
- 0491US8930625B2Weighted history allocation predictor algorithm in a hybrid cacheDALY DAVID M·Filed 2012·Granted Jan 6, 2015·14 cites·7 claims
- 0590US10489069B2Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory systemIBM·Filed 2017·Granted Nov 26, 2019·5 cites·25 claims
- 0690US8688915B2Weighted history allocation predictor algorithm in a hybrid cacheDALY DAVID M·Filed 2011·Granted Apr 1, 2014·12 cites·14 claims
- 0787US10395698B2Address/command chip controlled data chip address sequencing for a distributed memory buffer systemIBM·Filed 2017·Granted Aug 27, 2019·4 cites·14 claims
- 0887US9594647B2Synchronization and order detection in a memory systemIBM·Filed 2016·Granted Mar 14, 2017·4 cites·1 claims
- 0987US9355035B2Dynamic write priority based on virtual write queue high water mark for set associative cache using cache cleaner when modified sets exceed thresholdGLOBALFOUNDRIES INC·Filed 2013·Granted May 31, 2016·8 cites·20 claims
- 1086US10078461B1Partial data replay in a distributed memory buffer systemIBM·Filed 2017·Granted Sep 18, 2018·4 cites·1 claims
- 1185US8521982B2Load request scheduling in a cache hierarchyCARGNONI ROBERT A·Filed 2009·Granted Aug 27, 2013·26 cites·8 claims
- 1281US11269561B2Speculative bank activate dynamic random access memory (DRAM) schedulerIBM·Filed 2020·Granted Mar 8, 2022·1 cites·20 claims
- 1381US9170639B2Method and apparatus for mitigating effects of memory scrub operations on idle time power savings modesIBM·Filed 2013·Granted Oct 27, 2015·5 cites·12 claims
- 1479US9218292B2Least-recently-used (LRU) to first-dirty-member distance-maintaining cache cleaning schedulerIBM·Filed 2013·Granted Dec 22, 2015·4 cites·11 claims
- 1579US8909874B2Memory reorder queue biasing preceding high latency operationsBRITTAIN MARK A·Filed 2012·Granted Dec 9, 2014·5 cites·14 claims
- 1679US8788757B2Dynamic inclusive policy in a hybrid cache hierarchy using hit rateDALY DAVID M·Filed 2011·Granted Jul 22, 2014·5 cites·23 claims
- 1778US11372703B1Reduced system memory latency via a variable latency interfaceIBM·Filed 2021·Granted Jun 28, 2022·1 cites·19 claims
- 1876US9378144B2Modification of prefetch depth based on high latency eventIBM·Filed 2013·Granted Jun 28, 2016·3 cites·8 claims
- 1975US11042325B2Speculative bank activate dynamic random access memory (DRAM) schedulerIBM·Filed 2019·Granted Jun 22, 2021·1 cites·17 claims
- 2072US11042312B2DRAM bank activation managementIBM·Filed 2019·Granted Jun 22, 2021·1 cites·20 claims
- 2171US9384136B2Modification of prefetch depth based on high latency eventIBM·Filed 2013·Granted Jul 5, 2016·2 cites·19 claims
- 2271US9213647B2Least-recently-used (LRU) to first-dirty-member distance-maintaining cache cleaning schedulerIBM·Filed 2013·Granted Dec 15, 2015·2 cites·6 claims
- 2371US9086997B2Memory uncorrectable error handling technique for reducing the impact of noiseIBM·Filed 2013·Granted Jul 21, 2015·2 cites·14 claims
- 2471US9086998B2Memory uncorrectable error handling technique for reducing the impact of noiseIBM·Filed 2013·Granted Jul 21, 2015·2 cites·7 claims
- 2569US8996824B2Memory reorder queue biasing preceding high latency operationsIBM·Filed 2013·Granted Mar 31, 2015·2 cites·7 claims
- 2668US9632954B2Memory queue handling techniques for reducing impact of high-latency memory operationsBRITTAIN MARK A·Filed 2011·Granted Apr 25, 2017·2 cites·28 claims
- 2765US8140756B2Information handling system with immediate scheduling of load operations and fine-grained access to cache memoryGAI SANJEEV·Filed 2009·Granted Mar 20, 2012·4 cites·21 claims
- 2864US10976939B2Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory systemIBM·Filed 2019·Granted Apr 13, 2021·0 cites·20 claims
- 2964US9231618B2Early data tag to allow data CRC bypass via a speculative memory data return protocolIBM·Filed 2013·Granted Jan 5, 2016·1 cites·7 claims
- 3063US11157411B2Information handling system with immediate scheduling of load operationsIBM·Filed 2019·Granted Oct 26, 2021·0 cites·20 claims
- 3162US8843707B2Dynamic inclusive policy in a hybrid cache hierarchy using bandwidthDALY DAVID M·Filed 2011·Granted Sep 23, 2014·1 cites·18 claims
- 3260US11687254B2Host synchronized autonomous data chip address sequencer for a distributed buffer memory systemIBM·Filed 2019·Granted Jun 27, 2023·0 cites·16 claims
- 3360US10572168B2DRAM bank activation managementIBM·Filed 2017·Granted Feb 25, 2020·1 cites·20 claims
- 3457US10489293B2Information handling system with immediate scheduling of load operationsGHAI SANJEEV·Filed 2009·Granted Nov 26, 2019·1 cites·20 claims
- 3557US10353606B2Partial data replay in a distributed memory buffer systemIBM·Filed 2017·Granted Jul 16, 2019·0 cites·15 claims
- 3656US9495254B2Synchronization and order detection in a memory systemIBM·Filed 2016·Granted Nov 15, 2016·0 cites·1 claims
- 3755US11520659B2Refresh-hiding memory system staggered refreshIBM·Filed 2020·Granted Dec 6, 2022·0 cites·20 claims
- 3855US10534555B2Host synchronized autonomous data chip address sequencer for a distributed buffer memory systemIBM·Filed 2017·Granted Jan 14, 2020·0 cites·20 claims
- 3954US2015143059A1Dynamic write priority based on virtual write queue high water markIBM·Filed 2013·Application pending·0 cites
- 4053US2014052936A1Memory queue handling techniques for reducing impact of high-latency memory operationsIBM·Filed 2013·Application pending·0 cites
- 4152US10740031B2Interface scheduler for a distributed memory systemIBM·Filed 2018·Granted Aug 11, 2020·0 cites·17 claims
- 4251US11587600B2Address/command chip controlled data chip address sequencing for a distributed memory buffer systemIBM·Filed 2019·Granted Feb 21, 2023·0 cites·20 claims
- 4351US9164572B2Method and apparatus for mitigating effects of memory scrub operations on idle time power savings modeIBM·Filed 2014·Granted Oct 20, 2015·0 cites·7 claims
- 4450US8543759B2Method for scheduling memory refresh operations including power statesIBM·Filed 2013·Granted Sep 24, 2013·0 cites·6 claims
- 4549US10380040B2Memory request scheduling to improve bank group utilizationIBM·Filed 2017·Granted Aug 13, 2019·0 cites·17 claims
- 4645US9106258B2Early data tag to allow data CRC bypass via a speculative memory data return protocolIBM·Filed 2013·Granted Aug 11, 2015·0 cites·11 claims
- 4743US10747442B2Host controlled data chip address sequencing for a distributed memory buffer systemIBM·Filed 2017·Granted Aug 18, 2020·0 cites·20 claims
- 4841US8489807B2Techniques for performing refresh operations in high-density memoriesDODSON JOHN S·Filed 2010·Granted Jul 16, 2013·0 cites·10 claims
- 4940US8539146B2Apparatus for scheduling memory refresh operations including power statesBRITTAIN MARK A·Filed 2011·Granted Sep 17, 2013·0 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →