Dynamic write priority based on virtual write queue high water mark

Abstract

A set associative cache is managed by a memory controller which places writeback instructions for modified (dirty) cache lines into a virtual write queue, determines when the number of the sets containing a modified cache line is greater than a high water mark, and elevates a priority of the writeback instructions over read operations. The controller can return the priority to normal when the number of modified sets is less than a low water mark. In an embodiment wherein the system memory device includes rank groups, the congruence classes can be mapped based on the rank groups. The number of writes pending in a rank group exceeding a different threshold can additionally be a requirement to trigger elevation of writeback priority. A dirty vector can be used to provide an indication that corresponding sets contain a modified cache line, particularly in least-recently used segments of the corresponding sets.

1 . A method of managing a cache memory of a computer system comprising:
 loading memory values into cache lines of the cache memory wherein the cache lines are logically organized into sets according to different congruence classes;   modifying memory values in selected cache lines;   placing writeback instructions for modified cache lines into a virtual write queue of a system memory device;   determining that a number of the sets containing at least one modified cache line is greater than a predetermined threshold; and   responsive to said determining, elevating a priority of the writeback instructions.   
     
     
         2 . The method of  claim 1  wherein the cache memory is a lowest level cache memory in a memory hierarchy of the computer system. 
     
     
         3 . The method of  claim 1  wherein said elevating raises the priority of the writeback instructions over read operations. 
     
     
         4 . The method of  claim 1  further comprising:
 after elevating the priority of the writeback instructions, second determining that a second number of the sets containing at least one modified cache line is less than a second predetermined threshold; and 
 responsive to said second determining, lowering the priority of the writeback instructions. 
 
     
     
         5 . The method of  claim 1  wherein the system memory device includes a plurality of ranks forming different rank groups, and the congruence classes are mapped based on the rank groups. 
     
     
         6 . The method of  claim 5  wherein said determining is a first determining and the predetermined threshold is a first predetermined threshold, and further comprising second determining that a number of writeback instructions for a given rank group is greater than a second predetermined threshold, said elevating being further responsive to said second determining. 
     
     
         7 . The method of  claim 1  wherein said determining uses a dirty vector comprised of a plurality of bits providing an indication that corresponding sets contain at least one modified cache line. 
     
     
         8 . The method of  claim 7  wherein the bits in the dirty vector provide an indication that corresponding sets contain at least one modified cache line in a least-recently used segment of the corresponding sets. 
     
     
         9 - 24 . (canceled)