Inventor

BALAKRISHNAN KARTHIK

US317 patents

⚠️ This page may combine multiple inventors who share the name “BALAKRISHNAN KARTHIK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BALAKRISHNAN KARTHIK

IBM

Stacked complementary FETs featuring vertically stacked horizontal nanowires

Fabrication of nano-sheet transistors with different threshold voltages

Vertical field effect transistor with wrap around metallic bottom contact to improve contact resistance

Fabrication of strained vertical P-type field effect transistors by bottom condensation

Multiple gate length vertical field-effect-transistors

Replacement III-V or germanium nanowires by unilateral confined epitaxial growth

Channel-last replacement metal-gate vertical field effect transistor

Vertical transistor with air gap spacers

Lateral bipolar junction transistor with controlled junction

Stacked vertical transport field effect transistor electrically erasable programmable read only memory (EEPROM) devices

Stacked nanosheet field effect transistor floating-gate EEPROM cell and array

Nano-sheet transistors with different threshold voltages

Diode connected vertical transistor

Programmable read only memory (ROM) integrated in tight pitch vertical transistor structures

Tight pitch inverter using vertical transistors

Dual strained nanosheet CMOS and methods for fabricating

Tapered vertical FET having III-V channel

Floating gate memory in a channel last vertical FET flow

Vertical floating gate memory with variable channel doping profile

Co-fabrication of vertical diodes and fin field effect transistors on the same substrate

Vertical field effect transistor with undercut buried insulating layer to improve contact resistance

High density programmable e-fuse co-integrated with vertical FETs

Vertical transistors having different gate lengths

Self-aligned sigma extension regions for vertical transistors

III-V vertical field effect transistors with tunable bandgap source/drain regions

Nanosheet CMOS with hybrid orientation

Stacked nanowires with multi-threshold voltage solution for pFETs

Stacked nanosheets by aspect ratio trapping

Highly scaled tunnel FET with tight pitch and method to fabricate same

Vertical transistor pass gate device

Low voltage (power) junction FET with all-around junction gate

Channel-last replacement metal-gate vertical field effect transistor

Vertical field effect transistor including extension and stressors

Superlattice lateral bipolar junction transistor

Stacked nanowire devices formed using lateral aspect ratio trapping

Gate all-around FinFET device and a method of manufacturing same

Stacked nanosheet rom

Stacked-nanosheet semiconductor structures

Fabrication of vertical fin transistor with multiple threshold voltages

Twin gate field effect diode

Thin-base high frequency lateral bipolar junction transistor

Diode connected vertical transistor

Diode connected vertical transistor

Stacked FinFET EEPROM

Structure featuring ferroelectric capacitance in interconnect level for steep sub-threshold complementary metal oxide semiconductor transistors

Methods for removal of selected nanowires in stacked gate all around architecture

Methods for removal of selected nanowires in stacked gate all around architecture

Bipolar junction transistors and methods forming same

Large area electrostatic dischage for vertical transistor structures

GEN ELECTRIC

Polyarylate compositions