Inventor

FAROOQ MUKTA GHATE

US36 patents

⚠️ This page may combine multiple inventors who share the name “FAROOQ MUKTA GHATE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FAROOQ MUKTA GHATE

IBM

Interposer capacitor built on silicon wafer and joined to a ceramic substrate

Interposer capacitor built on silicon wafer and joined to a ceramic substrate

Temporary chip attach using injection molded solder

Structure and method for producing multiple size interconnections

Semiconductor device with early buried power rail (BPR) and backside power distribution network (BSPDN)

Stacked FET integration with BSPDN

Multiple die assembly

Structure and method for bridge chip assembly with capillary underfill

Semiconductor wafer having trenches with varied dimensions for multi-chip modules

Planar wafer level fan-out of multi-chip modules having different size chips

Assembly of a chip to a substrate

Substrate thinning for a backside power distribution network

Enhanced interconnect structure

Heterogeneous integration structure with voltage regulation

Heterogeneous integration of device die having BSPDN

TSV and backside power distribution structure

Sintering a nanoparticle paste for semiconductor chip join

High density interconnection and wiring layers, package structures, and integration methods

Bridge chip with through via

Memory and logic chip stack with a translator chip

Protective surface layer on under bump metallurgy for solder joining

Mitigating cooldown peeling stress during chip package assembly

Integration structure and planar joining

Cu—Cu bonding for interconnects on bridge chip attached to chips and packaging substrate

Simultaneous plating of varying size features on semiconductor substrate

Stacked semiconductor devices with topside and backside interconnect wiring

Infrared debond damage mitigation by copper fill pattern

Oxide-bonded wafer pair separation using laser debonding

Resist patterned redistribution wiring on copper polyimide via layer

Assembly of a chip to a substrate

Wafer dies with thermally conducting perimeter regions

Temperature hierarchy solder bonding

Semiconductor circuit power delivery

Structure and method to improve current-carrying capabilities of C4 joints

GLOBALFOUNDRIES INC

Post zero via layer keep out zone over through silicon via reducing BEOL pumping effects

YANG CHIH-CHAO

Enhanced interconnect structure