Inventor

MACNAMARA CHRIS

IE43 patents

⚠️ This page may combine multiple inventors who share the name “MACNAMARA CHRIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MACNAMARA CHRIS

INTEL CORP

Graphics processing unit (GPU) as a programmable packet transfer mechanism

Configuration of base clock frequency of processor based on usage parameters

Software-defined networking data re-direction

Technologies for performance monitoring and management with empty polling

Overload protection engine

Configuration of base clock frequency of processor based on usage parameters

Configuration of base clock frequency of processor based on usage parameters

Systems and methods for data service request classification and routing

Component redundancy systems, devices, and methods

Technologies for buffering received network packet data

Profiles for collecting telemetry data

Technologies for scalable packet reception and transmission

Techniques to manage cache resource allocations for a processor cache

Techniques for flow control packet processing

Techniques for routing packets within an evolved packet core

Configuration of base clock frequency of processor based on usage parameters

Scalable traffic management using one or more processor cores for multiple levels of quality of service

Mechanism to automatically prioritize I/O for NFV workloads at platform overload

Migration from a legacy network appliance to a network function virtualization (NFV) appliance

Technologies for providing efficient detection of idle poll loops

Remote register updates

Geographic service classification and routing

Platform slicing of central processing unit (CPU) resources

Geographic service classification and routing

Migration from a legacy network appliance to a network function virtualization (NFV) appliance

Technologies for performance monitoring and management with empty polling

Transient dataset management system

Dynamic traffic-aware interface queue switching among processor cores

System to monitor and control data in a network

Hierarchical reinforcement learning algorithm for NFV server power management

Network function virtualization architecture with device isolation

Dynamic maximum frequency limit for processing core groups

Technologies for scalable network packet processing with lock-free rings

Technologies for coordinating access to data packets in a memory

Technologies for power-aware scheduling for network packet processing

Technologies for extracting extrinsic entropy for workload distribution

Techniques to enable live migration of virtual environments

Networked peer device round-robin security controller

Techniques for a configuration mechanism of a virtual switch

Techniques for cache delivery

Technologies for monitoring health of a process on a compute device

SK HYNIX NAND PRODUCT SOLUTIONS CORP

Workload scheduler for memory allocation

MCLAUGHLIN BURSELL MICHAEL HINGSTON

Technologies for simulating service degradation in a software defined network