Inventor
DERBY JEFFREY H
US30 patents
⚠️ This page may combine multiple inventors who share the name “DERBY JEFFREY H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
25 patentsUS5426637AJun 20, 1995
Methods and apparatus for interconnecting local area networks with wide area backbone networks
IBM311 citations98
US5359593AOct 25, 1994
Dynamic bandwidth estimation and adaptation for packet communications networks
IBM262 citations97
US5483522AJan 9, 1996
Packet switching resource management within nodes
IBM72 citations96
US5425021AJun 13, 1995
Packet switching resource management within nodes
IBM72 citations96
US5309433AMay 3, 1994
Methods and apparatus for routing packets in packet transmission networks
IBM117 citations96
US5398012AMar 14, 1995
Distributed processing of route selection across networks and subnetworks
IBM69 citations95
US5365523ANov 15, 1994
Forming and maintaining access groups at the lan/wan interface
IBM57 citations95
US5274625ADec 28, 1993
Traffic measurements in packet communications networks
IBM65 citations95
US5311513AMay 10, 1994
Rate-based congestion control in packet communications networks
IBM69 citations94
US7631167B2Dec 8, 2009
System for SIMD-oriented management of register maps for map-based indirect register-file access
IBM8 citations84
US9740659B2Aug 22, 2017
Merging and sorting arrays on an SIMD processor
IBM7 citations82
US10042876B2Aug 7, 2018
Sort-merge-join on a large architected register file
IBM4 citations72
US9817612B2Nov 14, 2017
High-performance hash joins using memory with extensive internal parallelism
IBM2 citations71
US7855966B2Dec 21, 2010
Network congestion detection and automatic fallback: methods, systems and program products
IBM6 citations63
US8990281B2Mar 24, 2015
Techniques for improving the efficiency of mixed radix fast fourier transform
IBM2 citations62
US7360063B2Apr 15, 2008
Method for SIMD-oriented management of register maps for map-based indirect register-file access
IBM2 citations62
US11061675B2Jul 13, 2021
Vector cross-compare count and sequence instructions
IBM0 citations61
US10564964B2Feb 18, 2020
Vector cross-compare count and sequence instructions
IBM0 citations51
US9811287B2Nov 7, 2017
High-performance hash joins using memory with extensive internal parallelism
IBM1 citations51
US9047230B2Jun 2, 2015
Techniques for improving the efficiency of mixed radix fast fourier transform
IBM0 citations51
US11119766B2Sep 14, 2021
Hardware accelerator with locally stored macros
IBM0 citations50
US9710310B2Jul 18, 2017
Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines
IBM0 citations50
US9606838B2Mar 28, 2017
Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines
IBM0 citations50
US9584178B2Feb 28, 2017
Correlating pseudonoise sequences in an SIMD processor
IBM0 citations40
US10248419B2Apr 2, 2019
In-memory/register vector radix sort
IBM0 citations39