Methods and apparatus for dynamically switching processor mode

Abstract

In a first aspect, a first processing method is provided. The first processing method includes the steps of (1) operating a processor in a first mode based on an operand size associated with a first instruction received by the processor; and (2) dynamically switching the processor operation mode from the first mode to a second mode based on a different operand size associated with a second instruction received by the processor. Numerous other aspects are provided.

1. A processing method, comprising:
 operating a processor in a first mode based on an operand size associated with a first instruction received by the processor; and 
 dynamically switching the processor operation mode from the first mode to a second mode based on a different operand size associated with a second instruction received by the processor, 
 wherein the dynamic switching comprises switching the processor operation mode without bringing a processor system to a quiescent state. 
 
     
     
       2. The method of  claim 1  wherein operating the processor in the first mode based on the operand size associated with the first instruction received by the processor includes operating the processor in the first mode based on a page attribute indicating the operand size associated with the first instruction. 
     
     
       3. The method of  claim 2  wherein operating the processor in the first mode based on the operand size associated with the first instruction received by the processor further includes operating the processor in the first mode based on a cache line attribute indicating the operand size associated with the first instruction. 
     
     
       4. The method of  claim 1  wherein dynamically switching the processor operation mode from the first mode to the second mode based on the different operand size associated with the second instruction received by the processor includes dynamically switching the processor operation mode to the second mode based on a page attribute indicating the operand size associated with the second instruction. 
     
     
       5. The method of  claim 4  wherein dynamically switching the processor operation mode from the first mode to the second mode based on the different operand size associated with the second instruction received by the processor further includes dynamically switching the processor operation mode to the second mode based on a cache line attribute indicating the operand size associated with the second instruction. 
     
     
       6. The method of  claim 1  wherein:
 in the first mode of operation:
 a plurality of registers included in the processor store at least one operand associated with the first instruction; and 
 a plurality of execution units included in the processor operate on the stored at least one operand; and 
 
 in the second mode of operation:
 a register included in the processor stores at least one operand associated with the second instruction; and 
 at least one execution unit included in the processor operates on the stored at least one operand associated with the second instruction. 
 
 
     
     
       7. The method of  claim 1  wherein:
 in the first mode of operation:
 a register included in the processor stores at least one operand associated with the first instruction; and 
 at least one execution unit included in the processor operates on the stored at least one operand associated with the first instruction; and 
 
 in the second mode of operation:
 a plurality of registers included in the processor store at least one operand associated with the second instruction; and 
 a plurality of execution units included in the processor operate on the stored at least one operand associated with the second instruction.