Inventor

STOCKINGER MICHAEL A

US28 patents

⚠️ This page may combine multiple inventors who share the name “STOCKINGER MICHAEL A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STOCKINGER MICHAEL A

FREESCALE SEMICONDUCTOR INC

Electrostatic discharge circuit and method therefor

Shared ESD circuitry

Electrostatic discharge (ESD) clamp circuit with high effective holding voltage

Integrated circuit with protection from transient electrical stress events and method therefor

Pulse circuit using a transmission line

Transmission gate circuit

Sensing and detection of ESD and other transient overstress events

Distribution of electrostatic discharge (ESD) circuitry within an integrated circuit

Integrated circuit with protection from transient electrical stress events and method therefor

STOCKINGER MICHAEL A

Trigger circuit and method for improved transient immunity

Electrostatic discharge protection circuit for an integrated circuit

Transmission gate circuitry for high voltage terminal

Combined output buffer and ESD diode device

Overvoltage protection circuit for an integrated circuit

Integrated circuit electrical protection device

High frequency interconnect pad structure

Integrated circuit electrical protection device

NXP USA INC

Circuit for controlling a stacked snapback clamp

Electronic switch

Snapback clamps for ESD protection with voltage limited, centralized triggering scheme

Area-efficient ESD protection inside standard cells

Method and system for improved noise isolation in an electrostatic discharge protection scheme

High voltage interface circuit

Switch control circuit for a power switch with electrostatic discharge (ESD) protection

Integrated circuit with protection from transient electrical stress events and method therefor

TRAVIS EDWARD O

Integrated circuit design using pre-marked circuit element object library

PRAKASH SIDDI JAI

Tamper detector power supply with wake-up

NXP BV

Double IO pad cell including electrostatic discharge protection scheme with reduced latch-up risk