Transmission gate circuit

Abstract

A transmission gate circuit includes a pass gate and a control circuit and provides High Voltage protection to a flash memory in a characterization mode and a low resistive path with true open-drain functionality in a normal mode. A native NMOSFET in series with the pass gate provides overvoltage protection for additional circuitry. Well biasing, gate tracking and internal node clamping circuits ensure that all of the devices of the pass gate and control circuit operated within safe operational voltage levels. The two modes of operation can be selected by an enable signal. The transmission gate circuit can support up to a 5.5 volts input in a true open drain mode while an input/output supply voltage of 3.3 volts is supplied.

The invention claimed is: 
     
       1. A transmission gate circuit, comprising:
 an input node and an output node (I/O SIGNAL); 
 a first switching device having a first electrode coupled to the input node, a second electrode coupled to a nodal point, and a control electrode; 
 a switching stage having a first electrode coupled to the control electrode of the first switching device, a control electrode for receiving a first enable signal ENABLE, and a second electrode for connection to a first reference voltage VSS; 
 a second switching device having a first electrode coupled to the control electrode of the first switching device, a second electrode for receiving a first bias voltage NW, and a third electrode for receiving a control signal; and 
 a clamping circuit operably coupled to the nodal point for, when enabled, limiting the voltage level at the nodal point to a value equal to a sum of a second bias voltage NW 2 , and a threshold voltage, wherein the clamping circuit comprises:
 a fourth switching device having a first electrode, a second electrode coupled to the nodal point, and a control electrode for receiving the second bias voltage NW 2 ; and 
 a fifth switching device having a first electrode coupled to the first electrode of the fourth switching device, a second electrode for receiving the first reference voltage VSS, and a control electrode for receiving a second enable signal, 
 
 wherein when the first enable signal and the control signal are in a first state, the second switching device is off and the switching stage is on, pulling the control electrode of the first switching device to the first reference voltage VSS, and turning on the first switching device, thereby providing a conductive path between the input node and the nodal point, and 
 wherein when the first enable signal and the control signal are in a second state, the switching stage is off and the second switching device is on, pulling the control electrode of the first switching device to the first bias voltage NW, thereby putting the first switching device in a non-conductive state. 
 
     
     
       2. The transmission gate of  claim 1 , further comprising a protection device, including:
 a third switching device having a first electrode coupled to the output node, a second electrode coupled to the nodal point, and a control electrode connected to a supply voltage VDD, 
 wherein the third switching device provides a conductive path between the nodal point and the output node when the voltage at the nodal point is at or below the supply voltage VDD, and isolates the nodal point from the output node when the voltage at the nodal point is above the level of the supply voltage VDD. 
 
     
     
       3. The transmission gate circuit of  claim 2 , wherein the third switching device is a natural device comprising a NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor) having a negligible threshold voltage. 
     
     
       4. The transmission gate circuit of  claim 1 , wherein the fourth switching device comprises a P-channel metal oxide semiconductor field effect transistor (PMOSFET) and the fifth switching device comprises an N-channel MOSFET (NMOSFET) and wherein drain terminals of the fourth and fifth switching devices are connected to one another, a source terminal of the fourth switching device is connected to the nodal point, and a source terminal of the fifth switching device is connected to the first reference voltage VSS. 
     
     
       5. The transmission gate circuit of  claim 1 , further comprising a sixth switching device having a first electrode coupled to the input node, a second electrode coupled to the nodal point, and a control electrode for receiving the second bias voltage NW 2 , wherein the sixth switching device isolates the input node from the nodal point when a voltage level at the input node exceeds the second bias voltage NW 2 . 
     
     
       6. The transmission gate circuit of  claim 5 , wherein the sixth switching device comprises an N-channel metal oxide semiconductor field effect transistor (NMOSFET). 
     
     
       7. The transmission gate circuit of  claim 1 , further comprising:
 a bias voltage generating circuit for generating the first bias voltage NW, the second bias voltage NW 2 , and a third bias voltage HFV, each derived from a voltage level at the input node and from a second reference voltage, wherein the bias voltage generating circuit has a first input coupled to the input node and a second input for receiving the second reference voltage. 
 
     
     
       8. The transmission gate circuit of  claim 7 , wherein:
 the first bias voltage NW is equal to the higher of the voltage at the input node, and the second reference voltage, 
 the second bias voltage NW 2  is equal to the higher of half the voltage at the input node, and the second reference voltage, and 
 the third bias voltage HFV is equal to half the voltage at the input node. 
 
     
     
       9. The transmission gate circuit of  claim 1 , further comprising a level shifting circuit for providing the control signal at an output terminal thereof, wherein the control signal is derived from the first enable signal. 
     
     
       10. The transmission gate circuit of  claim 1 , wherein:
 the switching stage comprises first and second NMOSFETs (N-channel Metal Oxide Semiconductor Field Effect Transistor), 
 wherein the first NMOSFET has a drain terminal connected to the control electrode of the first switching device, a gate terminal that receives a second bias voltage NW 2 , and a source terminal connected to a transistor body of the first NMOSFET and to a drain terminal of the second NMOSFET, and 
 wherein the second NMOSFET has a source terminal connected to its transistor body and to the first reference voltage VSS, and a gate terminal that receives the first enable signal. 
 
     
     
       11. The transmission gate circuit of  claim 1 , wherein the first switching device comprises a P-channel metal oxide semiconductor field effect transistor (PMOSFET), wherein the control electrode comprises a gate terminal of the PMOSFET, a drain terminal of the PMOSFET is connected to the input node, and a source terminal of the PMOSFET is connected to the nodal point. 
     
     
       12. A transmission gate circuit, comprising:
 an input node and an output node (I/O SIGNAL); 
 a first switching device having a first electrode coupled to the input node, a second electrode coupled to a nodal point, and a control electrode; 
 a switching stage having a first electrode coupled to the control electrode of the first switching device, a control electrode for receiving a first enable signal ENABLE, and a second electrode for connection to a first reference voltage VSS; 
 a second switching device having a first electrode coupled to the control electrode of the first switching device, a second electrode for receiving a first bias voltage NW, and a third electrode for receiving a control signal; and 
 a level shifting circuit for providing the control signal at an output terminal thereof, wherein the control signal is derived from the first enable signal, 
 wherein when the first enable signal and the control signal are in a first state, the second switching device is off and the switching stage is on, pulling the control electrode of the first switching device to the first reference voltage VSS, and turning on the first switching device, thereby providing a conductive path between the input node and the nodal point, 
 wherein when the first enable signal and the control signal are in a second state, the switching stage is off and the second switching device is on, pulling the control electrode of the first switching device to the first bias voltage NW, thereby putting the first switching device in a non-conductive state, 
 wherein the level shifting circuit comprises: 
 seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth and fourteenth switching devices, wherein: 
 the seventh switching device has a first electrode connected to a first electrode of the eighth switching device and to the first bias voltage NW, a control electrode connected to the output terminal, and a second electrode connected to a control electrode of the eighth switching device and to a first electrode of the ninth switching device, 
 the eighth switching device has a second electrode connected to the output terminal, 
 control electrodes of the ninth and tenth switching devices are both connected to a third biasing voltage HFV, 
 the ninth switching device has a second electrode connected to a first electrode of the eleventh switching device, 
 the tenth switching device has a first electrode connected to the output terminal, and a second electrode connected to a first electrode of the twelfth switching device, 
 control electrodes of the eleventh and twelfth switching device are connected to the second bias voltage NW 2 , 
 the eleventh switching device has a second electrode connected to a first electrode of the thirteenth switching device, 
 the twelfth switching device has a second electrode connected to a first electrode of the fourteenth switching device, 
 second electrodes of the thirteenth and fourteenth switching devices are connected to the first reference voltage VSS, 
 the thirteenth switching device has a control electrode that receives the first enable signal, and 
 the fourteenth switching device has a control electrode that receives the second enable signal. 
 
     
     
       13. A transmission gate circuit, comprising:
 a pass gate connected between an input node and a nodal point; 
 a control circuit having an output connected to the pass gate, wherein the control circuit comprises: 
 a first switch having a first electrode connected to a first bias voltage NW; 
 a second switch having a first electrode connected to a second electrode of the first switch, and a control electrode that receives a second bias voltage NW 2 ; 
 a third switch having a first electrode connected to a second electrode of the second switch, a second electrode connected to a first reference voltage VSS, and a control electrode that receives a first enable signal ENABLE; 
 a level shifting circuit, connected between the first bias voltage NW and the first reference voltage VSS, that generates a control signal, wherein the control signal is derived from the first enable signal and is provided to a control electrode of the first switch of the control circuit; and 
 a clamping circuit connected between the nodal point and the first reference voltage VSS, wherein the clamping circuit, when enabled, limits the voltage level at the nodal point to a value equal to a sum of a second bias voltage NW 2 , and a threshold voltage. 
 
     
     
       14. The transmission gate circuit of  claim 13 , wherein the pass gate comprises:
 a first NMOSFET (N-channel metal oxide semiconductor field effect transistor) having a drain terminal connected to the input node, a source terminal connected to the nodal point and a gate terminal that receives a second bias voltage NW 2 ; and 
 a first PMOSFET (P-channel MOSFET) having a drain terminal connected to the input node and the drain terminal of the first NMOSFET, a source terminal connected to the nodal point and the source terminal of the first NMOSFET, and a gate connected to the output of the control circuit. 
 
     
     
       15. The transmission gate circuit of  claim 14 , further comprising a protection device having a first electrode coupled to an output node, a second electrode coupled to the nodal point, and a control electrode connected to a supply voltage VDD,
 wherein the protection device provides a conductive path between the nodal point and the output node when the voltage at the nodal point is at or below the supply voltage VDD, and isolates the nodal point from the output node when the voltage at the nodal point is greater than the supply voltage VDD. 
 
     
     
       16. The transmission gate circuit of  claim 15 , wherein the protection device comprises a second NMOSFET having a source terminal connected to the nodal point, a drain terminal connected to the output node for providing an output signal, and a gate terminal connected to the supply voltage VDD. 
     
     
       17. The transmission gate circuit of  claim 16 , wherein the clamping circuit comprises:
 a second PMOSFET having a source terminal connected to its body terminal and to the nodal point, and a gate terminal that receives the second bias voltage; and 
 a third NMOSFET having a drain terminal connected to a drain terminal of the second PMOSFET, a source terminal connected to its body and to the first reference voltage VSS, and a gate electrode that receives an inverted version of the enable signal. 
 
     
     
       18. The transmission gate of  claim 17 , wherein the first switch comprises a third PMOSFET, the second switch comprises a fourth NMOSFET and the third switch comprises a fifth NMOSFET, wherein:
 the third PMOSFET has a source terminal connected to a body of the third PMOSFET and to the first bias voltage NW; 
 the fourth NMOSFET has a drain terminal connected to a drain terminal of the third PMOSFET, and a gate terminal that receives the second bias voltage NW 2 ; 
 the fifth NMOSFET has a drain terminal connected to a source terminal of the fourth NMOSFET and a body of the fourth NMOSFET, a source terminal connected to a body of the fifth NMOSFET and to the first reference voltage VSS, and a gate terminal that receives the first enable signal ENABLE. 
 
     
     
       19. The transmission gate circuit of  claim 18 , wherein the level shifting circuit comprises:
 a fourth PMOSFET having a source terminal connected to its body and that receives the first bias voltage NW; 
 a fifth PMOSFET having a source terminal connected to its body and to the source terminal of the fourth PMOSFET, a drain terminal connected to a gate terminal of the fourth PMOSFET, and a gate terminal connected to a drain terminal of the fourth PMOSFET; 
 a sixth PMOSFET having a source terminal connected to its body and to the drain terminal of the fourth PMOSFET; 
 a seventh PMOSFET having a source terminal connected to its body and to the drain terminal of the fifth PMOSFET, wherein the control signal is generated at a node connected the drain of the fifth PMOSFET and the source of the seventh PMOSFET, and a gate terminal connected to a gate terminal of the sixth PMOSFET; 
 a sixth NMOSFET having a drain terminal connected to a drain terminal of the sixth PMOSFET; 
 a seventh NMOSFET having a drain terminal connected to a drain terminal of the seventh PMOSFET, and a gate terminal connected to a gate terminal of the sixth NMOSFET and to the second bias voltage NW 2 ; 
 an eighth NMOSFET having a drain terminal connected to a source terminal and a body of the sixth NMOSFET, a source electrode connected to a body of the eighth NMOSFET and the first reference voltage VSS, and a gate electrode that receives the first enable signal; and 
 a ninth NMOSFET having a drain terminal connected to a source terminal and a body of the seventh NMOSFET, a source terminal and a body connected to the first reference voltage VSS, and a gate electrode that receives the inverted version of the first enable signal.