Inventor

LIN MING-REN

US105 patents

⚠️ This page may combine multiple inventors who share the name “LIN MING-REN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIN MING-REN

ADVANCED MICRO DEVICES INC

FinFET device incorporating strained silicon in the channel region

FinFET device with multiple fin structures

Transistor with local insulator structure

Method of manufacturing a transistor with local insulator structure

CMOS optimization method utilizing sacrificial sidewall spacer

Fast Mosfet with low-doped source/drain

Dual damascene with a sacrificial via fill

Simplified dual damascene process for multi-level metallization and interconnection structure

Self aligned via dual damascene

Reversed T-shaped FinFET

Self aligned double gate transistor having a strained channel region and process therefor

Mosfets incorporating nickel germanosilicided gate and methods for their formation

Implantation into high-K dielectric material after gate etch to facilitate removal

Through wafer backside contact to improve SOI heat dissipation

Integrated circuit having transistors with different threshold voltages

Method of forming multiple levels of patterned metallization

Selective thinning of barrier oxide through masked SIMOX implant

Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant

Fabrication of dual gates of field transistors with prevention of reaction between the gate electrode and the gate dielectric with a high dielectric constant

Self aligned via dual damascene

Method of forming finned semiconductor devices with trench isolation

Semiconductor on insulator MOSFET having strained silicon channel

Damascene finfet gate with selective metal interdiffusion

Narrow fins by oxidation in double-gate finfet

Semiconductor-on-insulator transistor with recessed source and drain

Method for fabricating a MOSFET device structure which facilitates mitigation of junction capacitance and floating body effects

Low resistance salicide technology with reduced silicon consumption

High quality isolation for high density and high performance integrated circuits

Self-aligned silicide gate technology for advanced submicron MOS devices

Method of forming asymmetrically doped source/drain regions

Method for producing ultra-fine interconnection features

Advanced copper interconnect system that is compatible with existing IC wire bonding technology

Damascene process for reduced feature size

Subtractive dual damascene

Dual damascene with a protective mask for via etching

Suppression of boron segregation for shallow source and drain junctions in semiconductors

Heat removal in SOI devices using a buried oxide layer/conductive layer combination

Method for doping structures in FinFET devices

Semiconductor with tensile strained substrate and method of making the same

Strained silicon MOSFET having reduced leakage and method of its formation

Method for forming structures in finfet devices

Heat removal in SOI devices using a buried oxide layer/conductive layer combination

Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal

Embedded conductor for SOI devices using a buried conductive layer/conductive plug combination

STI (Shallow Trench Isolation) structures for minimizing leakage current through drain and source silicides

Low resistance composite contact structure utilizing a reaction barrier layer under a metal layer

Method of manufacturing a dual doped CMOS gate

Method of forming transistors with self aligned damascene gate contact

Integrated circuit having isolation structures

SPANSION LLC

Flash memory device