Self aligned double gate transistor having a strained channel region and process therefor

Abstract

A method of manufacturing an integrated circuit with a strained semiconductor channel region. The method can provide a double gate structure. The gate structure can be provided in and above a trench. The trench can be formed in a compound semiconductor material such as a silicon-germanium material. The strained semiconductor can increase the charge mobility associated with the transistor. A silicon-on-insulator substrate can be used.

1. A method of manufacturing an integrated circuit on a substrate including a compound semiconductor layer, the method comprising:
 providing a trench in the compound semiconductor layer;  
 providing a bottom gate in the trench; and  
 forming a strained semiconductor above the bottom gate and in the trench.  
 
     
     
       2. The method of  claim 1 , further comprising:
 providing a bottom dielectric layer intermediate the bottom gate and the strained semiconductor.  
 
     
     
       3. The method of  claim 2 , further comprising:
 providing a top dielectric layer above the strained semiconductor.  
 
     
     
       4. The method of  claim 1 , wherein the strained semiconductor is silicon. 
     
     
       5. The method of  claim 1 , wherein the strained semiconductor is laterally grown from the walls of the trench. 
     
     
       6. The method of  claim 5 , wherein the strained semiconductor layer is a silicon-germanium layer. 
     
     
       7. The method of  claim 1 , further comprising:
 providing recessed spacers in the trench before providing the bottom gate.  
 
     
     
       8. The method of  claim 7 , further comprising removing a top portion of the recessed spacers. 
     
     
       9. The method of  claim 1 , wherein the bottom gate conductor is deposited by CVD. 
     
     
       10. The method of  claim 1 , wherein the bottom gate conductor comprises polysilicon. 
     
     
       11. A transistor comprising:
 a first gate conductor disposed in a trench of a compound semiconductor layer;  
 a strained semiconductor layer disposed in the trench and above the first gate conductor; and  
 a second gate conductor disposed above the strained semiconductor layer and above the trench.  
 
     
     
       12. The transistor of  claim 11 , further comprising:
 a dielectric layer disposed between the first gate conductor and the strained semiconductor layer.  
 
     
     
       13. The transistor of  claim 11 , wherein the trench includes recessed spacers. 
     
     
       14. The transistor of  claim 11 , wherein the compound semiconductor layer is disposed above a buried oxide layer. 
     
     
       15. The transistor of  claim 11 , wherein the first gate conductor and the second gate conductor are each adjacent a dielectric layer. 
     
     
       16. The transistor of  claim 15 , wherein the compound semiconductor layer comprises silicon-germanium. 
     
     
       17. The transistor of  claim 15 , further comprising:
 a pair of dielectric spacers adjacent the first gate conductor and within the trench.  
 
     
     
       18. A process of forming a transistor having a strained silicon channel region, the process comprising:
 forming a trench in a compound semiconductor material;  
 forming a first gate at a bottom portion of the trench;  
 growing strained silicon above the first gate for the strained silicon channel region; and  
 forming a second gate above the strained silicon.  
 
     
     
       19. The process of  claim 18 , further comprising:
 providing spacers in the trench.  
 
     
     
       20. The process of  claim 19 , wherein the growing step is a lateral growing step.