Inventor

SHIELDS JEFFREY A

US71 patents

⚠️ This page may combine multiple inventors who share the name “SHIELDS JEFFREY A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHIELDS JEFFREY A

ADVANCED MICRO DEVICES INC

Process for reducing the critical dimensions of integrated circuit device features

Process for forming sub-lithographic photoresist features by modification of the photoresist surface

Process for preventing deformation of patterned photoresist features

Spacer narrowed, dual width contact for charge gain reduction

Double self-aligning shallow trench isolation semiconductor and manufacturing method therefor

Method of using a silicon oxynitride ARC for final metal layer

Integrated circuit with metal features presenting a larger landing area for vias

HSQ with high plasma etching resistance surface for borderless vias

HSQ dielectric interlayer

UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL

Fabrication of shallow trench isolation structures with rounded corner and self-aligned gate

Memory wordline hard mask

Punch-through via with conformal barrier liner

Flash memory with less susceptibility to charge gain and charge loss

Borderless vias with HSQ gap filled patterned metal layers

Borderless vias with HSQ gap filled patterned metal layers

Water vapor plasma for effective low-k dielectric resist stripping

Buried silicide local interconnect with sidewall spacers and method for making the same

Utilization of a Ta-containing cap over copper to facilitate concurrent formation of copper vias and memory element structures

Flash NVROM devices with UV charge immunity

Dual temperature nitride strip process

Borderless vias without degradation of HSQ gap fill layers

Spacer etch method for semiconductor device

Etch damage repair with thermal annealing

Memory with disposable ARC for wordline formation

Dual width contact for charge gain reduction

Method of forming narrow insulating spacers for use in reducing minimum component size

Specialized metal profile for via landing areas

Modified product mask for bridging detection

Native oxide removal with fluorinated chemistry before cobalt silicide formation

H2 diffusion barrier formation by nitrogen incorporation in oxide layer

Pad etch process capable of thick titanium nitride arc removal

Phosphoric acid process for removal of contact BARC layer

HSQ with high plasma etching resistance surface for borderless vias

HSQ dielectric interlayer

Method of prevention of degradation of low dielectric constant gap-fill material

Method of forming high integrity vias

UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing

High selectivity pad etch for thick topside stacks

Method to fabricate a high coupling flash cell with less silicide seam problem

Tapered isolated metal profile to reduce dielectric layer cracking

Efficient in-situ resist strip process for heavy polymer metal etch

Buried silicide local interconnect with sidewall spacers and method for making the same

High throughput plasma resist strip process for temperature sensitive applications

MICROCHIP TECH INC

Method for minimizing program disturb in a memory cell

Programming method for a memory cell

EEPROM memory cell with low voltage read path and high voltage erase/write path

SPANSION LLC

UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory devices in BEOL processing

Ultraviolet radiation blocking interlayer dielectric

ADVANCE MICRO DEVICES INC

Method for selective removal of ONO layer