Tapered isolated metal profile to reduce dielectric layer cracking

Abstract

Leading and trailing metal features in a dense array of conductive lines bordering an open field are formed with side surfaces that gradually taper in the direction of the open field toward an underlying substrate. Each side surface bordering the open field is formed with a sufficient slope to reduce cracking of the subsequently deposited dielectric gap fill layer at high stress areas bordering the open field.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor device, which method comprises: (a) forming a dense array of metal features, on a dielectric layer, including leading and trailing metal features each having a side surface bordering an open field, each side surface selectively gradually tapering in the direction of the open field toward an underlying substrate while the metal features between the leading and trailing metal features have side surfaces which extend substantially perpendicular to the substrate; and   (b) forming a layer of a dielectric material on the dense array of metal features filling the gaps, wherein each tapering side surface has a sufficient slope to substantially prevent cracking of the dielectric material proximate the side surfaces, wherein the metal features are spaced apart by a distance less than about one micron while the open field extends beyond about one micron.   
     
     
       2. The method according to claim 1, wherein the dielectric material comprises hydrogen silsesquioxane (HSQ). 
     
     
       3. The method according to claim 2, wherein each metal feature has a bottom surface and a top surface, which method comprises forming the dense array such that the width of the bottom surface of the leading and trailing metal features is about 10% to about 60% greater than the width of the top surface. 
     
     
       4. The method according to claim 3, comprising forming the dense array such that the width of the bottom surface of the leading and trailing metal features is about 20% to about 45% greater than the width of the top surface. 
     
     
       5. The method according to claim 2, wherein each side surface has a slope of about 35° to about 55° with respect to an upper surface of the substrate. 
     
     
       6. The method according to claim 5, wherein each side surface has a slope of about 45°. 
     
     
       7. The method according to claim 1, further comprising: forming an oxide layer on the dielectric material; and   planarizing the oxide layer.   
     
     
       8. The method according to claim 1, wherein the metal features are spaced apart by a distance less than about 0.5 microns. 
     
     
       9. The method according to claim 1, wherein the open field extends a distance greater than about 1.5 microns. 
     
     
       10. The method according to claim 1, comprising: forming a first dielectric layer;   forming a metal layer on the first dielectric layer;   forming a mask on the metal layer, which mask comprises a pattern defining a dense array of spaced apart metal features, including leading and trailing metal features each having a side surface bordering an open field;   etching the metal layer to form a pattern of metal features including the dense array, and controlling the etching to control the slope of the side surfaces; and   forming a second layer of a dielectric material on the metal pattern and on the first dielectric layer filling the spaces between the metal features.   
     
     
       11. The method according to claim 10, wherein the second dielectric layer comprises hydrogen silsesquioxane (HSQ). 
     
     
       12. The method according to claim 11, wherein each metal feature has a bottom surface and a top surface, which method comprises etching the metal layer such that the bottom surface of the leading and trailing metal features has a width of about 10% to about 60% greater than the width of top surface. 
     
     
       13. The method according to claim 12, comprising etching the metal layer such that the bottom surface of the leading and the trailing metal features has a width of about 20% to about 45% greater than the width of the top surface. 
     
     
       14. The method according to claim 11, wherein each side surface has a slope of about 35° to about 55° with respect to an upper surface of the first dielectric layer. 
     
     
       15. The method according to claim 14, wherein each side surface has a slope of about 45°. 
     
     
       16. The method according to claim 10, further comprising: depositing a third dielectric layer on the second dielectric layer; and   planarizing the third dielectric layer by etching or chemical-mechanical polishing.   
     
     
       17. The method according to claim 16, wherein the third dielectric layer comprises an oxide. 
     
     
       18. The method according to claim 10, further comprising reactive ion etching in a plasma to form the metal features; and   controlling the slope of the tapered side surface by controlling the amount of polymer formed during etching.   
     
     
       19. The method according to claim 18, comprising varying an amount of gaseous reactant, inert gas and/or pressure, to control the amount of polymer formed during etching. 
     
     
       20. The method according to claim 19, comprising varying the amount of nitrogen, fluorocarbon and/or chlorine to increase polymer formation during etching. 
     
     
       21. The method according to claim 20, comprising increasing the amount of nitrogen and/or fluorocarbon or decreasing the amount of chlorine to increase polymer formation during etching. 
     
     
       22. A semiconductor device comprising: (a) dense array of spaced apart metal features, on a dielectric layer, including leading and trailing metal features each having a side surface bordering an open field which selectively gradually tapers in the direction of the open field toward an underlying substrate while the metal features between the leading and trailing metal features have side surfaces which extend substantially perpendicular to the substrate; and   (b) a layer of a dielectric material deposited on the dense array of metal features filling the gaps, wherein each tapering side surface has a sufficient slope to prevent cracking of the deposited dielectric material proximate the side surface, wherein, the metal features are spaced apart by a distance less than about one micron while the open field extends beyond about one micron.   
     
     
       23. The semiconductor device according to claim 22, wherein the dielectric material comprises hydrogen silsesquioxane (HSQ). 
     
     
       24. The semiconductor device according to claim 23, wherein each metal feature has a bottom and a top surface, and the bottom surface of the leading and trailing metal features has a width about 10% to about 60% greater than the width of the top surface. 
     
     
       25. The semiconductor device according to claim 24, wherein the bottom surface of the leading and trailing metal features has a width about 20% to about 45% greater than the width of the top surface. 
     
     
       26. The semiconductor device according to claim 25, wherein each side surface has a slope of about 35° to about 55° with respect to an upper surface of the substrate. 
     
     
       27. The semiconductor device according to claim 26, wherein each side surface has a slope of about 45°.