Inventor

REBER DOUGLAS M

US56 patents

⚠️ This page may combine multiple inventors who share the name “REBER DOUGLAS M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

REBER DOUGLAS M

REBER DOUGLAS M

Method for forming an electrical connection between metal layers

Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules

Semiconductor manufacturing for forming bond pads and seal rings

Method and system for derived layer checking for semiconductor device design

Semiconductor manufacturing using disposable test circuitry within scribe lanes

Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuit

Thin beam deposited fuse

Stress migration mitigation

Methods and apparatus to improve reliability of isolated vias

Method for forming an electrical connection between metal layers

Semiconductor device having a nanotube layer and method for forming

Semiconductor device with vias on a bridge connecting two buses

Method and apparatus to improve reliability of vias

Method for forming an electrical connection between metal layers

Method and apparatus to improve reliability of vias

Methods and apparatus to improve reliability of isolated vias

FREESCALE SEMICONDUCTOR INC

Teleconferencing environment having auditory and visual cues

Method for forming an integrated circuit having a programmable fuse

Method of forming inter-level dielectric structures on semiconductor devices

3D device packaging using through-substrate posts

Though-substrate vias (TSVs) and method therefor

Method for verifying design rule checks

Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures

Solar cell powered integrated circuit device and method therefor

Semiconductor device with graphene encapsulated metal and method therefor

3D device packaging using through-substrate pillars

3D device packaging using through-substrate posts

Semiconductor device with embedded heat spreading

Semiconductor device having a nanotube layer and method for forming

Stress migration mitigation utilizing induced stress effects in metal trace of integrated circuit device

Semiconductor device with vias on a bridge connecting two buses

SHROFF MEHUL D

Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failures

Device matching tool and methods thereof

Via placement and electronic circuit design processing method and electronic circuit design utilizing same

Capping layer interface interruption for stress migration mitigation

Multi-layer process-induced damage tracking and remediation

MOTOROLA INC

Method of forming semiconductor device including interconnect barrier layers

Anti-fuse circuit and method of operation

Integrated circuit having interconnect to a substrate and method therefor

NXP USA INC

Semiconductor package with embedded capacitor and methods of manufacturing same

Method of forming inter-level dielectric structures on semiconductor devices

Semiconductor device with graphene encapsulated metal and method therefor

TRAVIS EDWARD O

Integrated circuit design using pre-marked circuit element object library

Semiconductor device with embedded heat spreading

Semiconductor device with heat dissipation

PENN STATE RES FOUND

Low temperature, high quality silicon dioxide thin films deposited using tetramethylsilane (TMS) for stress control and coverage applications

Low temperature, high quality silicon dioxide thin films deposited using tetramethylsilane (TMS)

DELCO ELECTRONICS CORP

Solder paste and conductive ink printing stencil cleaner

AJURIA SERGIO A

Semiconductor package with embedded capacitor and methods of manufacturing same

ADVANCED MICRO DEVICES INC

Semiconductor device having an organic anti-reflective coating (ARC) and method therefor